MLC Flash Memory Partial Interleave for BER Equalization

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Solution Overview

Problem

Multi-level cell (MLC) flash memory devices face increased bit-error rates (BER) as the number of bits stored in each memory cell increases, leading to a disproportionate increase in resources required for error correction, particularly in the complexity, size, and operating time of the error correction code (ECC) circuit.

Innovation Solution

A nonvolatile memory system with N-bit MLC memory cells that divides data into M page groups, applies a partial interleave process to equalize the bit-error rate (BER) within each group, and adjusts threshold voltage distributions to reduce BER disproportion across groups, using a memory controller with an ECC circuit to generate parity bits and manage data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of bits stored in each memory cell is increased to achieve higher integration, then storage density is improved, but the bit-error rate increases and ECC circuit complexity increases

Engineering Contradiction:

Improvestorage densityVSAvoidECC circuit complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the N pages of data into M page groups, where each page group contains at least one page. This segmentation allows the ECC circuit to process data in smaller, manageable units rather than handling all N pages simultaneously, thereby reducing the complexity and resource requirements of the ECC circuit while maintaining effective error correction for high-density storage.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If the number of bits stored in each memory cell is increased, then storage density is improved, but the bit-error rate increases

Engineering Contradiction:

Improvestorage densityVSAvoidbit-error rate

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies different error correction strategies to different page groups based on their specific BER characteristics. By analyzing and treating each page group according to its local error profile rather than applying a uniform approach, the system optimizes error correction effectiveness for high-density storage while managing the overall BER.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent performs preliminary analysis of BER distribution across pages before applying error correction. By pre-dividing pages into groups and analyzing their error characteristics in advance, the system can apply targeted error correction measures that optimize reliability for high-density storage configurations.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If full interleave process is applied to equalize BER across all pages, then BER equalization is improved, but buffer memory capacity and processing time increase

Engineering Contradiction:

ImproveBER equalizationVSAvoidbuffer memory capacity

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies a partial interleave process that divides N pages into M page groups and processes only the necessary groups for error correction, rather than fully interleaving all pages. This partial action achieves sufficient BER equalization for practical purposes while significantly reducing the buffer memory capacity and processing time required compared to a complete interleave of all N pages.

Inventive Principle:

Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces BER disproportion across pages, optimizing ECC circuit resources and buffer memory capacity, while maintaining data integrity and reducing the complexity of the ECC circuit, thereby enhancing the performance and efficiency of MLC flash memory devices.

Implementation Method 1

the controller is configured to program the N pages of data into the MLC memory cells, and to execute a partial interleave process in which the N pages of data are divided into M page groups

Methodology Applied

Scientific EffectInterleave process:

Implementation Method 2

each of the M page groups is applied to an error correction code (ECC) circuit to generate parity bits for the respective M page groups

Methodology Applied

Scientific EffectError correction coding:

Implementation Method 3

this is accomplished by setting the threshold voltage (e.g., through Fowler-Nordheim tunneling) of each memory cell to within one of 2N threshold distributions

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Data Source

PatentUS8355279B2Nonvolatile memory device and system, and method of programming a nonvolatile memory device

Publication Date: 2013.01.15 SAMSUNG ELECTRONICS CO LTD

AI summary

A nonvolatile memory includes a plurality of N-bit multi-level cell (MLC) memory cells and a controller. The plurality of N-bit MLC memory cells are for storing N pages of data, each of the MLC memory cells programmable into any one of 2N threshold voltage distributions, where N is a positive number. The controller is configured to program the N pages of data into the MLC memory cells, and to execute a partial interleave process in which the N pages of data are divided into M page groups, where M is a positive number and where each page group includes at least one of the N pages of data, and in which each of the M page groups is applied to an error correction code (ECC) circuit to generate parity bits for the respective M page groups, where a bit-error rate (BER) among the pages within each of the M groups is equalized by the partial interleave process.