MLC Flash Memory Programming Method for Program Disturbance
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Solution Overview
Problem
In multi-level cell (MLC) flash memory devices, adjacent memory cells can be negatively affected during programming, leading to reduced reliability due to program disturbance, where memory cells intended to remain unprogrammed experience shifted threshold voltages.
Innovation Solution
A programming method that involves multiple programming operations on low pages of memory cells, including initial and secondary programming operations, using incremental step pulse programming (ISPP) with verification voltages to ensure accurate threshold voltage distribution, thereby minimizing program disturbance from adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If programming voltage is applied to memory cells to program them, then the memory cells can store data, but adjacent memory cells may experience threshold voltage shifts due to program disturbance
Solution Approach 1:
The programming process is divided into multiple sequential stages with different voltage levels. The patent applies a first programming voltage to program memory cells to an initial threshold voltage level, then applies a second programming voltage at a different level to adjust the threshold voltage to the target level. This segmentation allows precise control of threshold voltage distribution while minimizing disturbance to adjacent cells.
Solution Approach 2:
The patent performs preliminary programming operations on a first page of memory cells before programming a second page. By establishing the threshold voltage distribution of the first page in advance, the patent prevents program disturbance to the first page when programming the second page, as the verification process ensures adjacent cells remain within acceptable voltage ranges.
2Manufacturing precision
If multiple programming voltages are applied to achieve precise threshold voltage distribution, then programming precision is improved, but programming time increases
Solution Approach 1:
The patent implements periodic programming and verification cycles using incremental step pulse programming (ISPP). Programming voltages are applied in periodic increments with verification steps in between, allowing the system to efficiently converge to the target threshold voltage distribution. This periodic approach balances precision requirements with time efficiency by avoiding unnecessary voltage applications.
3Measurement precision
If verification voltage is applied to verify programming status, then programming accuracy is ensured, but additional time is consumed
Solution Approach 1:
The patent employs feedback mechanisms where verification results directly influence subsequent programming actions. After applying programming voltages, the system verifies the threshold voltage distribution and uses this feedback information to determine whether additional programming is needed and at what voltage level. This feedback loop ensures accurate programming while minimizing unnecessary verification cycles.
Data Source
AI summary
Provided is a programming method for a memory device including a memory array and a controller. The programming method including: controlling programming on a first page of a first word line by the controller; controlling programming on a first page of a second word line by the controller, the second word line being adjacent to the first word line; controlling for performing a first programming operation on a second page of the first word line by the controller; controlling programming on a first page of a third word line by the controller, the third word line being adjacent to the second word line; controlling for performing the first programming operation on a second page of the second word line by the controller; and controlling for performing a second programming operation on the second page of the first word line by the controller.