Multi-Level Cell Flash Programming Sequence for Interference Reduction
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Solution Overview
Problem
Multi-level cell (MLC) flash memory devices face issues with floating gate coupling and threshold voltage drift due to the close proximity of memory cells, leading to data corruption and high bit error rates, especially in applications requiring large storage capacity.
Innovation Solution
Implementing a programming sequence where pages with the most-significant bit (MSB) and central significant bit (CSB) are programmed first, followed by the least-significant bit (LSB), and utilizing additional buffer memories to accommodate this sequence, which reduces floating gate coupling interference and threshold voltage drift by programming neighboring cells before the target cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC memory cell size is decreased to increase storage capacity, then storage capacity is improved, but floating gate coupling and threshold voltage drift increase
Solution Approach 1:
The patent applies preliminary action by programming neighboring cells before programming the target cell. This sequence is established in advance to prevent floating gate coupling interference and threshold voltage drift that would occur if target cells were programmed first. The programming order is predetermined and executed systematically across the memory array.
Solution Approach 2:
The patent inverts the conventional programming approach by programming neighboring cells first instead of programming the target cell first. This reversal of the normal programming sequence eliminates the harmful floating gate coupling effect that occurs when adjacent cells are programmed after the target cell, thereby protecting data integrity while maintaining high storage capacity.
2Reliability
If neighboring cells are programmed before target cell to reduce interference, then data integrity is improved, but programming complexity increases
Solution Approach 1:
The patent segments the programming operation into distinct phases: first programming neighboring cells, then programming the target cell. This segmentation is applied systematically across the memory array, dividing the programming task into manageable units that can be executed in the required sequence without excessive complexity.
Solution Approach 2:
The patent uses buffer memories as intermediaries to manage the complex programming sequence. These buffers temporarily store programming data and coordinates, enabling the controller to execute the multi-stage programming process (neighboring cells first, then target cell) without requiring complex real-time coordination logic.
3Reliability
If MSB and CSB pages are programmed first followed by LSB pages, then floating gate coupling interference is reduced, but programming time increases
Solution Approach 1:
The patent applies preliminary action by programming MSB and CSB pages before LSB pages, establishing the correct programming sequence in advance. This preliminary programming of higher-significance bits first creates the proper electrical conditions that minimize floating gate coupling interference during subsequent LSB programming, thereby reducing signal distortion.
Solution Approach 2:
The patent uses periodic action by organizing the programming process into distinct stages corresponding to different bit significances (MSB stage, CSB stage, LSB stage). Each stage is executed as a separate periodic programming pass, allowing systematic management of the multi-bit programming process while minimizing interference effects.
Data Source
AI summary
Systems, methods and computer program products for minimizing floating gate coupling interference and threshold voltage drift associated with flash memory cells are described. In some implementations, the memory cells can be programmed in a predetermined sequence that allows pages with the most-significant bit (MSB) and central significant bit (CSB) to be programmed first prior to programming pages with the least-significant bit (LSB). This sequence allows neighboring cells (e.g., cells neighboring a target cell) to be programmed first so as to reduce the floating gate coupling interference and threshold voltage drift on the target cell that is to be programmed in the subsequent stage. To accommodate the programming sequence (e.g., at the device level), additional buffer memories can be added.