Parallel MLC Flash Programming via SRAM Bit Pairing
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Solution Overview
Problem
The existing programming methods for flash multiple level cell (MLC) memory are inefficient, resulting in decreased programming speed due to serial programming of each level, which requires multiple steps and verification processes.
Innovation Solution
Implementing a parallel programming method where all four levels of the MLC are programmed simultaneously by loading data into a SRAM, pairing bits, and applying voltages to the drain side of transistors in memory cells using a power control circuit, allowing for simultaneous programming of '00', '01', and '10' levels while '11' is maintained as the default state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If serial programming method is used for MLC memory, then programming process is simple and reliable, but programming speed is slow due to multiple sequential steps
Solution Approach 1:
The patent segments the programming process into distinct phases: data preparation phase (loading into SRAM and pairing bits), verification phase (reading and comparing), and programming phase (applying voltages only to cells needing programming). This segmentation allows parallel processing of multiple bit pairs while maintaining clear control over the complex process, resolving the contradiction between speed and complexity.
Solution Approach 2:
The patent performs preliminary actions by loading all data into SRAM and pairing bits before the actual programming operation. This pre-processing allows the system to identify which bit pairs need programming and prepare verification data in advance, enabling faster execution of the programming step without sacrificing reliability.
2Loss of time
If serial programming of each level is performed, then verification is reliable, but programming time increases due to multiple programming cycles
Solution Approach 1:
The patent merges the programming of multiple levels into a single parallel operation. By loading data into SRAM, pairing bits from different words, and applying voltages simultaneously to multiple memory cells, the system achieves fast programming while maintaining verification reliability through immediate read-back and comparison of the programmed data.
3Productivity
If multiple programming steps are used for four-level MLC, then data accuracy is ensured, but productivity decreases due to repeated programming cycles
Solution Approach 1:
The patent implements feedback by immediately reading back the programmed data and comparing it with the original data from SRAM. This verification step provides feedback on programming success, allowing the system to ensure data accuracy while maintaining high productivity by avoiding unnecessary repeated programming cycles for correctly programmed cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases programming speed by allowing all bit pairs to be written and verified in parallel, reducing the number of programming cycles and improving overall data writing efficiency.
Implementation Method 1
A channel region lies under the floating gate, with an insulation layer in the form of a tunnel oxide layer between the channel and floating gate
Implementation Method 2
The energy barrier of the tunnel oxide can be overcome by applying a sufficiently high electric field across the tunnel oxide
Implementation Method 3
This allows electrons to pass through the tunnel oxide, thus changing the number of electrons stored in the floating gate
Data Source
AI summary
Methods and apparatus are provided for programming a flash multiple level memory cell (MLC) memory. The method may include loading data into an SRAM. The method may include reading a plurality of multiple-bit words from the data in the SRAM and loading the words into at least one latch buffer of a power control circuit. The method may also include pairing one or more bits from one of the words in the latch buffer with one or more bits from another of the words in the latch buffer and determining which of the bit pairs require programming. Moreover, the method may include programming, in parallel, each memory cell with the determined bit pairs. The method may further include programming each multiple level memory cell by applying a voltage to the drain side of a transistor of the memory cells corresponding to the determined bit pairs.