Voltage Reference Selection for MLC Flash Memory Read Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices experience data read errors due to charge loss and device wear, leading to performance degradation and reduced endurance, as existing heroic error recovery methods cause significant read latency and are not effective in extending storage subsystem endurance.
Innovation Solution
Implementing a background voltage reference testing process that selects and updates voltage reference values proactively, reducing bit error counts by performing non-host-initiated read operations and caching optimal values for use in host-based reads, thereby minimizing performance impact and extending the storage subsystem's useful life.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heroic error recovery is used to recover data when bit errors exceed ECC correction capability, then data reliability is improved, but read latency increases significantly and performance specifications are not met
Solution Approach 1:
The patent performs voltage reference testing and adjustment in advance during background operations before host read operations occur. By proactively optimizing voltage reference values and identifying problematic memory blocks beforehand, the system ensures that when host read operations occur, the voltage references are already optimized, eliminating the need for time-consuming heroic error recovery during actual data reads.
Solution Approach 2:
The patent extracts the error recovery process from the critical host read path by performing voltage reference testing and adjustment during idle background periods. This separates the time-consuming optimization operations from the performance-critical data read operations, allowing heroic error recovery mechanisms to be prepared in advance without impacting real-time read performance.
2Reliability
If heroic error recovery is performed to extend storage subsystem endurance, then data recovery capability is improved, but the storage subsystem falls below performance specifications
Solution Approach 1:
The system performs voltage reference optimization and error recovery preparation in advance during background operations. By proactively adjusting voltage reference values and identifying blocks that may require heroic recovery before host access occurs, the system maintains high data recovery capability while ensuring that actual host read operations complete quickly without performance degradation.
Solution Approach 2:
The patent removes the performance impact of error recovery operations from the host read path by performing all voltage reference testing and adjustment during idle background periods. This extraction ensures that the storage subsystem meets performance specifications for host operations while maintaining robust error recovery capabilities through pre-performed optimization.
3Measurement precision
If voltage reference values are adjusted dynamically to reduce bit errors, then read accuracy is improved, but system complexity increases
Solution Approach 1:
The patent implements a self-service mechanism where the storage subsystem automatically performs voltage reference testing, analysis, and adjustment without requiring external intervention. The system monitors its own performance metrics, identifies when voltage reference optimization is needed, and autonomously adjusts the values during background operations, thereby improving read accuracy while maintaining simple operation for the host system.
Solution Approach 2:
The system performs voltage reference optimization in advance during background operations before host read operations occur. By proactively adjusting voltage reference values based on monitored error rates and device wear, the system improves read accuracy while keeping the complexity hidden from the host, as all adjustments are made automatically during idle periods.
Data Source
AI summary
A storage subsystem implements a background process for selecting voltage reference values to use for reading data from a non-volatile memory array, such as an array of multi-level cell (MLC) flash memory. The process involves performing background read operations using specific sets of voltage reference values while monitoring the resulting bit error counts. The selected voltage reference values for specific pages or other blocks of the array are stored in a table. Read operations requested by a host system are executed using the corresponding voltage reference values specified by the table.