MLC Nonvolatile Memory Programming with Adaptive Verification
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Solution Overview
Problem
Multi-level cell (MLC) nonvolatile memory devices face reliability issues due to the need for increased operational precision when storing multiple bits per cell, leading to less reliable data storage as the number of bits increases.
Innovation Solution
A method and device that apply different verification voltages and program loops to manage slow bits, allowing for flexible programming and adjusting verification voltages based on the number of slow bits and program loops to improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell (MLC) programming is used to store more than one bit per cell, then storage capacity increases, but data reliability decreases due to greater operational precision requirements
Solution Approach 1:
The patent applies different verification voltages and slow bit tolerances to different target states (T0, T1, T2, T3) based on their threshold voltage ranges. By adjusting verification parameters and tolerance levels for each state, the system maintains high storage capacity while improving reliability through state-specific optimization rather than uniform programming constraints
Solution Approach 2:
The patent divides the programming process into separate program loops for different target states, with each loop having customized verification voltages and slow bit tolerance settings. This segmentation allows independent optimization of each state's programming parameters, enabling high-capacity MLC storage while maintaining reliability through targeted verification strategies for each threshold voltage range
2Manufacturing precision
If verification voltage is increased to improve programming precision, then manufacturing precision improves, but the number of program loops increases reducing productivity
Solution Approach 1:
The patent dynamically adjusts verification voltages based on the target state being programmed. Different verification voltages are applied to different target states (T0, T1, T2, T3) according to their specific threshold voltage ranges, allowing each state to be verified with optimal voltage levels rather than using a single high verification voltage for all states, thus maintaining precision while reducing overall programming time
Solution Approach 2:
The patent applies local quality by assigning different slow bit tolerances to different target states based on their characteristics. Each target state has a customized tolerance level that matches its threshold voltage range and programming requirements, allowing precision to be optimized locally for each state without uniformly increasing verification stringency across all states, thereby maintaining productivity
3Reliability
If slow bit tolerance is increased to improve reliability, then data reliability improves, but measurement precision requirements increase
Solution Approach 1:
The patent changes verification parameters by applying different verification voltages and slow bit tolerances to different target states. This parameter differentiation allows the system to accommodate higher slow bit tolerances for certain states without compromising overall verification precision, as each state is verified with parameters optimized for its specific threshold voltage range and error characteristics
Data Source
AI summary
A method of programming selected memory cells to a plurality of target states comprises applying a first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to at least one target state, applying a program voltage to the selected memory cells, and applying a second verification voltage lower than the first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to the at least one target state, wherein the second verification voltage is provided in a specified program loop and subsequent program loops. The second verification voltage is set such that a number of slow bits in the at least one target state is different from the number of slow bits in another target state.