1.5-bit MLC Memory Array for In-Memory Computation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in achieving accurate and fast in-memory computation due to current distribution overlaps during MAC operations and the use of multi-level cells, which lead to reduced computation accuracy and speed, as well as increased bit-line-setup times and reading errors.
Innovation Solution
Implementing a memory device with a 1.5-bit multi-level cell (MLC) memory array that divides threshold voltage distribution into fewer states and reduces bit-line setups, allowing for improved computation accuracy and speed by storing MSB and LSB vectors separately and performing bit-line setups only once.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cells (MLC) are used to store data with more states, then storage capacity is improved, but voltage intervals narrow and reading errors increase
Solution Approach 1:
The patent divides each memory unit into two separate bits (first bit and second bit) to store MSB and LSB vectors separately. This segmentation allows the system to use fewer threshold voltage states (N<4) per memory unit while maintaining 2-bit storage capacity, thereby widening voltage intervals and reducing reading errors without sacrificing storage capacity.
2Speed
If analog MAC operation is performed in memory array, then computation speed is improved, but current distribution overlaps cause misjudgment and reduce computation accuracy
Solution Approach 1:
The patent replaces the analog current-based MAC operation with a digital reading operation. By storing MSB and LSB vectors in separate bits and performing digital reads, the system eliminates current distribution overlaps that cause misjudgment in analog operations, while maintaining computational efficiency through the streamlined bit-line setup process.
3Measurement precision
If multiple bit-line-setups are performed to read data from memory array, then reading accuracy is improved, but setup time increases and computation speed decreases
Solution Approach 1:
The patent merges the reading operations for MSB and LSB vectors into a single bit-line-setup process. By designing the memory array such that both bits can be read simultaneously through one setup, the system eliminates the need for multiple sequential setups, thereby reducing setup time and increasing computation speed while maintaining reading accuracy through the separate bit structure.
Data Source
AI summary
A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.