Multi-Level Cell Memory Device Bit-Line Grouping
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Solution Overview
Problem
Conventional ROM designs face challenges in achieving increased bit-density and lower power consumption, particularly as SoC designs become more complex, leading to metal routing congestion and higher power consumption.
Innovation Solution
The proposed memory device uses multiple memory cells grouped to jointly store multiple bits, with a peripheral circuit that reads first bits from each memory cell through bit-line groups and determines second bits by jointly considering these first bits, allowing for increased bit-density and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell (MLC) ROM cells are used to increase bit-density, then bit-density is improved, but bit-line metal routing congestion occurs leading to larger cell area, slower performance, and higher power consumption
Solution Approach 1:
The patent segments the bit-line routing into multiple groups, where each group serves a specific subset of memory cells. This segmentation allows bit-lines to be distributed across multiple groups rather than all bit-lines serving all cells, reducing congestion in any single routing path while maintaining high bit-density through MLC structure
Solution Approach 2:
The patent introduces a group dimension to the bit-line organization, where bit-lines are arranged in groups that can be selectively activated. This dimensional organization allows for more efficient routing by activating only the necessary bit-line groups for a given memory cell access, reducing overall routing congestion
2Quantity of substance
If ROM capacity is increased to support complex SoC designs, then storage capacity is improved, but die size increases leading to larger chip area and higher power consumption
Solution Approach 1:
The patent merges multiple memory cells into MLC structures where multiple bits are stored in a single cell area. This merging approach increases ROM capacity without proportionally increasing chip area, as multiple bits share the same physical storage space through the MLC configuration
Solution Approach 2:
The patent implements a universal memory cell structure that can store multiple bits through MLC configuration. This multi-functional cell design allows a single cell area to serve multiple storage purposes, increasing capacity efficiency while maintaining compact chip area
3Quantity of substance
If conventional MLC ROM cells are used to increase bit-density, then bit-density is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic bit-line group activation where only the necessary bit-line groups are activated for a given memory access operation. This dynamic approach reduces the total number of active bit-lines compared to conventional MLC designs, thereby lowering power consumption while maintaining high bit-density
Data Source
AI summary
A memory device includes memory cells, at least one word-line, bit-line groups, and a peripheral circuit. Each bit-line group includes multiple bit-lines. The peripheral circuit obtains first bits by reading the memory cells through the bit-line groups, respectively, when the memory cells are selected by the at least one word-line; and determines second bits stored in the memory cells by jointly considering the first bits. The number of the memory cells is smaller than the number of the second bits.