Multi-Level Cell Memory Block Erasure Marking via Upper Page Reprogramming
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Solution Overview
Problem
Current NAND flash memory devices require a lengthy process to mark blocks for erasure, and there is a need for a method to program pages within a block more than once, especially when power is removed from the controller, necessitating a way to store erasure information within the block itself.
Innovation Solution
The method allows reprogramming of bits in the upper page from a '1' to a '0' to mark a block for erasure, enabling efficient block management by initializing both pages to '1' and then programming the lower page first, followed by specific programming of the upper page, allowing for multiple programming instances without violating existing rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a block is marked for erasure by traditional methods, then the block can be erased, but the process takes 2 to 3 milliseconds during which the device cannot be used for other operations
Solution Approach 1:
The patent applies preliminary action by marking blocks for erasure in advance during normal programming operations. Instead of initiating erasure immediately when needed, the controller identifies and marks candidate blocks during idle periods or alongside other operations, so that when erasure is actually required, the block is already prepared and can be erased immediately without delaying other device operations.
2Adaptability or versatility
If pages within a block are programmed multiple times, then block management flexibility improves, but traditional rules prevent reprogramming once a page is programmed
Solution Approach 1:
The patent applies segmentation by dividing the block into multiple pages and further segmenting the marking process. Instead of marking the entire block at once, the system can mark individual pages or portions of pages for erasure. This allows selective reprogramming of specific pages while maintaining others, enabling multiple programming cycles within a block without requiring complete block erasure and thereby improving management flexibility.
Solution Approach 2:
The patent applies dynamics by making the erasure marking process dynamic rather than static. Blocks transition between different states (available, marked for erasure, being erased) based on real-time needs and usage patterns. The controller can dynamically adjust which blocks are marked for erasure based on wear leveling algorithms, performance metrics, and operational requirements, allowing the system to adapt to changing conditions without rigid constraints.
Data Source
AI summary
A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function.