Multi-Level Cell Memory Density via Charge State Segmentation
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in increasing memory density beyond storing 2 bits per cell, as they struggle to efficiently manage multiple charge states and current levels for higher bit storage.
Innovation Solution
The implementation of a Multi-Level Cell (MLC) technique in band-to-band (BTB) PHINES memory cells, which allows for storing 4 bits per cell by utilizing different charge states in a nitride layer and employing current amplifiers or multiple sensing voltages to detect these states, enabling more precise control over current flow and logic states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor memory devices store only 2 bits per cell, then the device complexity and manufacturing process remain simple, but the memory density is limited
Solution Approach 1:
The patent applies parameter changes by utilizing multiple charge states (different quantities of trapped holes) in the nitride layer to represent multiple bits per cell. Instead of binary states, the memory cell stores data by varying the number of trapped charges, enabling 4 bits per cell storage while using the same physical cell structure.
Solution Approach 2:
The patent transitions from binary (2-state) to multi-level (4-state) storage by adding a dimensional aspect to the charge storage capability. Each cell can now exist in four distinct charge states rather than two, effectively adding a dimension to the data representation capability without increasing physical cell count.
2Quantity of substance
If multiple charge states are used to increase bits per cell, then memory density increases, but the precision of detecting current levels becomes more difficult
Solution Approach 1:
The patent segments the detection process into multiple discrete steps, applying different read voltages sequentially to distinguish between different charge states. Each voltage level probes a specific range of charge states, allowing the system to identify the precise state of each cell through a series of binary decisions rather than attempting to measure continuous current levels in one step.
Solution Approach 2:
The patent uses multiple read voltage levels (excessive action) to ensure accurate detection of charge states. By applying more voltage levels than the minimum required, the system can more reliably distinguish between adjacent charge states and correct for variations in cell characteristics, thereby improving measurement precision.
3Quantity of substance
If 4 bits per cell storage is implemented, then data storage capacity increases, but the physical size reduction benefit is offset by increased programming and sensing complexity
Solution Approach 1:
The patent makes the existing memory cell structure multi-functional by enabling it to perform both 2-bit and 4-bit storage modes using the same physical components. The nitride layer and transistor structure serve multiple purposes: they can store different quantities of charge to represent different bit values, and the same cell can be programmed and read using extended versions of existing operations rather than requiring entirely new mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases memory density by allowing each memory cell to store multiple bits, enhancing data storage capacity while reducing physical size and improving error detection through precise current threshold comparisons.
Implementation Method 1
Programming of the memory cell is achieved by hot hole injection into nitride layer 110
Implementation Method 2
the charge accumulated on nitride layer 110 can be erased by a process known as Fowler-Nordheim Injection
Implementation Method 3
The tunneling through the bottom or top oxide layer can occur in the presence of a high electric field, created as a result of application of the erase voltages to transistor 100, and is a form of quantum mechanical tunneling
Data Source
AI summary
A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.