Multi-Level Cell Memory Data Path with Bit Mapping Circuit
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Solution Overview
Problem
Current semiconductor memory systems face challenges in increasing capacity without significantly increasing size, particularly in accurately storing, reading, and writing multiple memory states beyond traditional power-of-two configurations, which complicates the manufacturing process and costs.
Innovation Solution
The implementation of a data path with a bit mapping and data conversion circuit that enables storage of non-power-of-two memory states per cell, allowing for a non-integer number of bits per cell by using groups of multi-level memory cells, effectively increasing storage density without the limitations of traditional power-of-two state systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are designed to store multiple bits of digital information by accurately storing, reading, and writing four distinct memory states, then storage capacity increases, but manufacturing complexity increases resulting in increased cost
Solution Approach 1:
The patent segments the storage system into multiple memory cells that can be independently configured. Each memory cell can be programmed to store a specific number of states (2, 3, 4, or more), allowing the system to achieve high storage capacity through combinations of cells rather than requiring each cell to store a large number of states, thereby reducing manufacturing complexity while maintaining high capacity
Solution Approach 2:
The patent implements dynamic configuration where memory cells can be programmed to operate with different numbers of states based on system requirements. This flexibility allows the system to optimize between storage capacity and manufacturing complexity by selecting appropriate state configurations for different cell groups, rather than being locked into a fixed high-complexity multi-state design
2Quantity of substance
If memory cells store more than two memory states to increase storage density beyond one bit per cell, then storage density increases, but the difficulty of reliably and accurately storing, reading, and writing memory states increases
Solution Approach 1:
The patent divides the storage array into multiple memory cells, each storing a manageable number of states (2-4 states per cell). This segmentation distributes the reliability burden across many simple cells rather than requiring a few complex high-state cells, improving overall reliability while maintaining high storage density through the collective capacity of the segmented cells
Solution Approach 2:
The patent uses partial action by having memory cells store more states than the minimum required for integer bits per cell (e.g., 3 states instead of 2 for 1 bit). This allows the system to achieve high storage density while keeping individual cell complexity low, and the excess states provide redundancy that can improve reliability through error correction schemes
3Quantity of substance
If the number of memory states per memory cell is increased to store more bits per cell, then storage capacity increases, but the complexity of the data path and control circuitry increases
Solution Approach 1:
The patent segments data storage across multiple memory cells, each handling a limited number of states. The data path complexity is distributed and managed at the cell level rather than requiring complex centralized circuitry for high-state cells, reducing overall data path complexity while achieving high storage capacity through the combined capacity of segmented cells
Solution Approach 2:
The patent changes the dimensional approach from increasing states within a single cell to increasing the number of cells operating in parallel with fewer states each. This dimensional shift from vertical (more states per cell) to horizontal (more cells) scaling reduces data path complexity by using simpler, more numerous cell units rather than complex high-state cells
Data Source
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AI summary
Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array.