MLC Memory ECC Placement by Bit Level and Error Rate
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Solution Overview
Problem
Traditional solid-state memory devices face inefficiencies in programming and reading operations due to their binary nature, which becomes increasingly troublesome as more bits are stored on each multi-level cell (MLC), leading to longer operation times and susceptibility to errors.
Innovation Solution
The memory devices utilize threshold voltage ranges to represent multiple data values, allowing for single read and write operations that handle complete bit patterns rather than discrete bits, and employ analog voltage signals to store and retrieve data, enabling efficient storage and retrieval of multiple bits per cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored on each multi-level cell, then storage density increases, but operation time increases due to binary read/write limitations
Solution Approach 1:
The patent replaces the binary digital read/write mechanism with an analog voltage-based mechanism. Instead of performing multiple sequential binary operations to read/write multi-bit data from MLCs, the system uses analog voltage levels to directly represent and transfer complete bit patterns in a single operation, eliminating the sequential bottleneck
Solution Approach 2:
The patent changes the parameter representation from discrete binary values (0 or 1) to continuous analog voltage levels. Each voltage level within a threshold range represents a specific multi-bit pattern, allowing the system to encode and decode multiple bits simultaneously through analog-to-digital and digital-to-analog conversion processes
2Quantity of substance
If multiple bits are stored on each multi-level cell, then storage capacity increases, but error rate increases due to reduced threshold margins
Solution Approach 1:
The patent replaces the binary comparison-based read mechanism with an analog voltage measurement system. By measuring the actual analog voltage level rather than comparing against multiple binary thresholds, the system can more accurately determine the stored bit pattern and reduce misinterpretation errors
Solution Approach 2:
The patent introduces analog voltage signals as an intermediary between the stored data and the read operation. The analog voltage serves as a direct representation of the bit pattern, eliminating the need for multiple binary comparisons and reducing the accumulation of errors that occur in sequential binary operations
3Ease of operation
If traditional binary read operations are used, then simplicity is maintained, but multiple read operations are required increasing complexity
Solution Approach 1:
The patent merges multiple binary read operations into a single analog read operation. Instead of performing separate reads for each bit position and then combining the results, the system performs one analog voltage measurement that directly yields the complete multi-bit pattern through analog-to-digital conversion
Solution Approach 2:
The patent creates a universal read mechanism that can retrieve complete multi-bit patterns through a single operation regardless of the number of bits stored per cell. The analog voltage-based approach works uniformly for 2-bit, 3-bit, or higher capacity MLCs, eliminating the need for operation sequences that scale with bit count
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces operation times and enhances reliability by allowing a single read operation to return multiple bits of information, improving storage capacity and reducing error rates in multi-level cell devices.
Implementation Method 1
The memory devices utilize threshold voltage ranges to represent multiple data values, allowing for single read and write operations that handle complete bit patterns rather than discrete bits
Implementation Method 2
employ analog voltage signals to store and retrieve data, reducing the need for multiple program and read operations
Data Source
AI summary
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.