MLC Memory ECC Encoding with Delayed Parallel Code Generation
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Solution Overview
Problem
Conventional multi-level cell (MLC) memory devices face challenges in increasing storage density and reliability due to limited voltage windows, leading to higher read-failure rates as the number of bits stored in a single memory cell increases.
Innovation Solution
The implementation of a new error correction method using a code encoding and decoding apparatus that includes a delay circuit and a code generator to generate an n·p-bit code based on input and delayed information, reducing encoding and decoding time, and incorporating an inner and outer encoder/decoder scheme to improve ECC performance and reduce hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in a single memory cell increases, then storage density is improved, but read-failure rate increases and reliability deteriorates
Solution Approach 1:
The patent divides the error correction task into two independent stages: inner error correction (IEC) for correcting errors within a page, and outer error correction (OEC) for correcting remaining errors across multiple pages. This segmentation allows each decoder to operate with simplified logic, improving reliability while maintaining high storage density through efficient parallel processing
Solution Approach 2:
The patent transitions from traditional single-level cell (SLC) one-dimensional error correction to multi-level cell (MLC) two-dimensional error correction by organizing data into a matrix structure with rows and columns. This dimensional change enables independent row and column decoding operations, improving both storage density and reliability through enhanced error detection and correction capabilities
2Quantity of substance
If the number of bits stored in a single memory cell increases, then storage density is improved, but voltage window requirements increase making manufacturing more difficult
Solution Approach 1:
The patent changes the voltage parameter strategy by implementing separate read voltage levels for even and odd rows (Vread_even and Vread_odd). This parameter differentiation allows the MLC memory to maintain stable threshold voltage distributions across multiple bits per cell without requiring excessively wide voltage windows, thereby improving manufacturability while achieving high storage density
3Reliability
If conventional error correction methods are used, then reliability is maintained, but encoding and decoding time increases
Solution Approach 1:
The patent segments the error correction process into parallel inner and outer decoding operations that can be executed simultaneously. The inner error correction decoder processes page-level errors while the outer error correction decoder handles cross-page errors, significantly reducing total decoding time compared to sequential conventional methods while maintaining comprehensive error correction capability
Solution Approach 2:
The patent performs preliminary error correction at the inner level before outer decoding is needed. By correcting the majority of errors within each page first through IEC, the remaining error burden for OEC is dramatically reduced, enabling faster overall decoding while maintaining high reliability
4Reliability
If conventional error correction methods are used, then error correction is achieved, but hardware complexity increases
Solution Approach 1:
The patent divides the error correction hardware into separate inner and outer decoder modules with distinct functional responsibilities. This segmentation allows each module to use simpler, more efficient algorithms tailored to its specific error correction needs, reducing overall hardware complexity compared to a single monolithic error correction system while maintaining comprehensive error correction capability
Data Source
AI summary
A code encoding apparatus includes a delay circuit and a code generator. The delay circuit generates delayed information based on p-bit input information received in parallel. The delayed information is generated according to a clock. The code generator generates n·p-bit code based on at least one of the input information and the delayed information, where n is a rational number.