MLC Memory ECC Placement by Cell Bit Level and Error Rate
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Solution Overview
Problem
Traditional solid-state memory devices face inefficiencies in programming and reading operations due to their binary nature, which becomes cumbersome as more bits are stored per cell, leading to longer operation times and increased susceptibility to errors as the bits per cell count increases.
Innovation Solution
The memory devices utilize a multi-level cell (MLC) approach where threshold voltage ranges represent multiple data states, allowing for a single read operation to return an analog signal indicative of the complete data value or bit pattern, rather than requiring multiple operations to determine individual bits, and incorporate error correction code (ECC) by varying the bit level per cell based on actual error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored on each multi-level cell, then storage density is improved, but operation time increases and error susceptibility worsens
Solution Approach 1:
The patent segments the programming and reading operations into distinct phases: a first programming operation programs initial data values, followed by a second programming operation that programs additional data values by adjusting threshold voltage ranges. Similarly, reading operations are segmented into multiple passes with different read thresholds. This segmentation allows complex multi-bit operations to be broken down into manageable steps, reducing overall operation time while maintaining high storage density.
Solution Approach 2:
The patent employs dynamic read thresholds that change based on the programming state. After the first programming operation, a first read threshold is used; after the second programming operation, a second read threshold is applied. This dynamic adjustment of read thresholds enables the system to efficiently distinguish between different data states stored in the multi-level cell, reducing reading time and improving operation efficiency while maintaining high storage density.
2Quantity of substance
If multiple bits are stored on each multi-level cell, then storage density is improved, but error susceptibility increases
Solution Approach 1:
The patent performs preliminary programming operations before final data storage. The first programming operation programs initial data values and establishes baseline threshold voltage ranges. The second programming operation then builds upon this foundation by programming additional data values. This preliminary action ensures that each programming step starts from a known, stable state, reducing the likelihood of programming errors and improving overall data reliability while maintaining high storage density.
Solution Approach 2:
The patent incorporates verification steps between programming operations and uses dynamic read thresholds to detect and correct reading errors. After the first programming operation, a verification read is performed using the first read threshold. Similarly, after the second programming operation, another verification is performed using the second read threshold. This feedback mechanism allows the system to detect and correct errors in real-time, improving data reliability while maintaining high storage density.
3Productivity
If threshold voltage ranges are used to represent multiple data values, then single read and write operations are enabled, but programming complexity increases
Solution Approach 1:
The patent changes the parameter space by using threshold voltage ranges instead of discrete voltage levels. Each data value is represented by a specific range of threshold voltages rather than a single value. This parameter change allows the system to store multiple bits per cell while using relatively simple programming and reading operations, as the operations only need to determine which range the threshold voltage falls into, rather than precisely controlling or measuring specific voltage values.
Solution Approach 2:
The patent transitions from a one-dimensional representation (single bit per cell with binary voltage levels) to a two-dimensional representation (multiple bits per cell with threshold voltage ranges). By adding the dimension of voltage range width to the traditional voltage level concept, the system can encode multiple bits of information while maintaining relatively simple programming and reading operations. The programming operation adjusts the threshold voltage to fall within the appropriate range, and the reading operation determines which range the voltage occupies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces operation times and enhances reliability by allowing a single read operation to represent multiple bits and adaptively adjusting the bit level for error correction, thereby improving storage efficiency and accuracy.
Implementation Method 1
The memory devices utilize threshold voltage ranges to represent multiple data values, allowing for single read and write operations that handle complete bit patterns rather than discrete bits
Data Source
AI summary
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.