Multi-Level Cell Memory Erased Page Verification

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Solution Overview

Problem

Existing flash memory systems face challenges in reliably verifying the erased or programmed state of memory cells, as flags used for indication may not be reliable, and Error Correction Code (ECC) analysis alone may not ensure that memory cells are truly unwritten, leading to potential data loss or corruption during programming.

Innovation Solution

A method involving multiple verification steps, including reading flag bits, performing ECC analysis, and counting cells not in an erased state, with subsequent reads using different voltages to confirm the program/erase condition, ensures accurate identification of memory cell states, preventing incorrect data overwrite.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If ECC analysis is used to verify memory cell states, then verification speed is improved, but reliability of verifying erased state is insufficient

Engineering Contradiction:

Improveverification speedVSAvoidaccuracy of verifying erased state

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The verification process is divided into multiple independent verification steps: first verifying using ECC analysis for speed, then performing a second verification by counting the number of cells in non-erased states to ensure reliability. This segmentation allows each verification method to perform its specialized function without compromising the other.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system uses feedback from the first verification (ECC analysis) to trigger a second verification step. If the first verification indicates a page is erased, the system then performs additional counting verification to confirm the erased state, using the results to feedback into the final verification decision.

Inventive Principle:

Principle #23Feedback

2Reliability

If multiple verification steps are implemented, then reliability of verifying memory cell states is improved, but device complexity increases

Engineering Contradiction:

Improveaccuracy of verifying memory cell statesVSAvoidcomplexity of verification process

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system performs preliminary verification using ECC analysis before implementing the more thorough but complex counting verification method. This preliminary action filters out obviously erased pages, so the complex second verification only needs to be performed when necessary, reducing overall system complexity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of always performing the full complex verification process, the system applies partial verification (ECC analysis only) when sufficient, and only applies excessive verification (both methods) when the first verification indicates potential issues or when high reliability is required.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS8887011B2Erased page confirmation in multilevel memory

Publication Date: 2014.11.11 SANDISK TECHNOLOGIES LLC

AI summary

In a multi-level cell memory array, a flag that indicates that a logical page is unwritten is subject to a two-step verification. In a first verification step, the logical page is read, and ECC decoding is applied. If the first verification step indicates that the logical page is unwritten, then a second verification step counts the number of cells that are not in an unwritten condition.