Narrowing Threshold Voltage Distribution in MLC Memory Erase

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Solution Overview

Problem

In non-volatile memory devices with multi-level cells, the erase operation often results in widened threshold voltage distributions due to interference between memory cells, leading to inefficiencies and reduced performance.

Innovation Solution

A method is introduced that involves pre-programming cells to shift threshold voltage distributions to the highest level, followed by an erase operation, a soft program, and verifying operations to divide memory blocks into groups, allowing for targeted soft programming and verification to narrow the threshold voltage distribution and reduce interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an erase operation is performed on memory cells, then data is erased and threshold voltage is reduced, but threshold voltage distribution widens due to over-erase and interference effects

Engineering Contradiction:
Improveerase operation effectivenessVSAvoidthreshold voltage distribution width
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent divides the memory block into multiple segments and performs erase operations on different segments at different times. This segmentation approach reduces interference between memory cells during the erase process, preventing threshold voltage distribution widening while maintaining effective data erasure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs a preliminary soft program operation before the main erase operation to shift threshold voltage distributions to the highest level. This preliminary action ensures that all memory cells are in a consistent state before erasing, which prevents over-erase conditions and reduces threshold voltage distribution width.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If a soft program is performed to compensate over-erased cells, then threshold voltage is adjusted to desired level, but additional time and operations are required

Engineering Contradiction:
Improvethreshold voltage distribution widthVSAvoiderase operation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The soft program operation is performed as a preliminary step before the main erase operation, rather than as a corrective step after erasing. This timing optimization allows the threshold voltage distributions to be pre-aligned, reducing the need for extensive post-erase soft programming and thereby reducing total operation time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the soft program operation to be performed only on specific segments that require threshold voltage adjustment, rather than on the entire memory block. This targeted approach reduces the total number of operations required while maintaining precise threshold voltage control.

Inventive Principle:
Principle #1Segmentation

3Reliability

If verifying operation is performed on entire memory block, then erase completeness is confirmed, but operation time increases

Engineering Contradiction:
Improveerase operation completenessVSAvoidverifying operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The verifying operation is divided into multiple stages corresponding to different memory segments. Each segment is verified after its specific erase operation, allowing for targeted verification rather than verifying the entire block uniformly. This reduces total verification time while maintaining comprehensive coverage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Preliminary verification is performed on each segment before proceeding to the next erase operation. This staged verification approach identifies and addresses issues in specific segments early, preventing the need for re-verification of the entire block and reducing total operation time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7633813B2Method of performing an erase operation in a non-volatile memory device
Publication Date: 2009.12.15 SK HYNIX INC
  • US7633813B2 patent drawing
  • US7633813B2 patent drawing
  • US7633813B2 patent drawing

AI summary

An erase method of a memory cell array which includes at least one block having MLC is disclosed. The erase method includes shifting every threshold voltage distribution into a threshold voltage distribution having a highest level by pre-programming every cell in a block selected for erase, performing an erase operation on the pre-programmed memory block, performing a soft program and a verifying operation on the memory block, dividing the memory block into a first group and a second group when the memory block is passed, performing a verifying operation on the first group and performing a soft program and a verifying operation on the first group when the first group is not passed, and performing a verifying operation on the second group when the first group is passed and performing a soft program and a verifying operation on the second group when the second group is not passed.