MLC Memory Error Correction Using Error-to-Erasure Conversion
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Solution Overview
Problem
Current error correction techniques in memory devices, such as low-density parity-check (LDPC) codes, face challenges in achieving efficient code rates while maintaining processing times and avoiding latency issues, especially when dealing with errors in multi-level cell (MLC) memory systems.
Innovation Solution
The implementation of a tensor product code (TPC) that combines single parity check (SPC) and Bose-Chaudhuri-Hocquenghem (BCH) codes within an ECC encoder and decoder framework, allowing for higher code rates by converting errors to erasures and utilizing LDPC codes for correction, thereby enhancing error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher code rates are used to improve error correction, then error correction capability is improved, but processing time increases and latency problems occur
Solution Approach 1:
The patent segments the error correction process into two distinct phases: first converting errors to erasures using SPC and BCH codes, then correcting the erasures using LDPC codes. This segmentation allows each phase to be optimized independently, achieving high error correction capability while controlling processing time through efficient division of labor between different coding schemes.
Solution Approach 2:
The patent performs preliminary error-to-erasure conversion using SPC and BCH codes before applying LDPC correction. By converting errors to erasures in advance, the system prepares the data in a form that is more efficiently handled by LDPC codes, reducing the overall processing time required for complete error correction while maintaining high code rates.
2Reliability
If more redundant information bits are added to improve error correction, then error correction capability is improved, but code rate efficiency decreases
Solution Approach 1:
The patent divides redundant information into different functional layers: SPC and BCH codes provide initial error-to-erasure conversion with moderate redundancy, while LDPC codes provide additional correction capability. This layered segmentation allows the system to achieve high error correction capability while optimizing the distribution of redundant bits across different coding stages, improving overall code rate efficiency.
Solution Approach 2:
The patent changes the parameter of data representation by converting errors to erasures, which fundamentally alters how redundancy is utilized. This parameter change enables the system to achieve the same error correction capability with fewer redundant bits, as erasure correction is more efficient than general error correction, thereby improving code rate efficiency.
3Productivity
If tensor product code is implemented to convert errors to erasures, then code rate is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple established coding techniques (SPC, BCH, and LDPC) into a unified tensor product code framework. By combining these proven methods, the system achieves high code rates and error-to-erasure conversion capability while leveraging the existing simplicity and efficiency of each individual coding scheme, thereby managing device complexity through integration of familiar components.
4Reliability
If LDPC codes are used for error correction, then error correction capability is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary error-to-erasure conversion using computationally lighter SPC and BCH codes before applying LDPC correction. This preliminary action reduces the burden on the LDPC decoder by converting difficult error correction problems into simpler erasure correction problems, thereby reducing LDPC decoding latency while maintaining high error correction capability.
Solution Approach 2:
The patent segments the correction task so that SPC and BCH codes handle the initial error detection and conversion, while LDPC codes focus specifically on erasure correction. This segmentation allows LDPC to operate more efficiently on a reduced problem set, decreasing processing time and latency compared to using LDPC alone for complete error correction.
Data Source
AI summary
Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.