MLC Memory Coding Scheme for High-Density Error Correction
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Solution Overview
Problem
Conventional Multi-Level Cell (MLC) memory devices face challenges in increasing storage density due to reliability issues and high read failure rates as the number of bits stored in a single memory cell increases, leading to a decrease in threshold voltage difference between neighboring bits.
Innovation Solution
The implementation of a concatenated coding scheme using both outer and inner encoders and decoders, which includes block coding for burst error correction and convolutional coding for random error correction, allows for dynamic adjustment of error correction overhead and enables storage of more than four bits in a single memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in a single memory cell increases, then storage density is improved, but read failure rate increases and reliability deteriorates
Solution Approach 1:
The patent divides the error correction process into two independent segments: an outer encoder performing block coding for burst error correction, and an inner encoder performing convolutional coding for random error correction. This segmentation allows each coding scheme to specialize in correcting specific types of errors, thereby improving overall reliability while maintaining high storage density in MLC memory cells.
2Quantity of substance
If the number of bits stored in a single memory cell increases, then storage density is improved, but voltage window requirements increase making manufacturing more difficult
Solution Approach 1:
The patent changes the approach to error correction by introducing a dual coding scheme with different code rates and types. The outer block code and inner convolutional code work together to correct errors without requiring larger voltage windows, thus enabling higher storage density while maintaining manufacturability within existing voltage constraints.
3Reliability
If error correction overhead is increased to improve reliability, then read failure rate decreases, but device complexity increases
Solution Approach 1:
The patent segments the error correction functionality into two distinct coding layers: outer block coding for burst errors and inner convolutional coding for random errors. This segmentation allows the system to achieve comprehensive error correction with manageable complexity, as each encoder handles specific error types rather than requiring a single complex coding scheme to handle all error types.
Solution Approach 2:
The dual coding scheme provides multi-functionality by simultaneously addressing both burst errors and random errors through two different coding approaches. This universal error correction capability improves reliability without requiring separate systems for different error types, thereby managing device complexity effectively.
Data Source
AI summary
A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.