MLC NAND Memory Controller Using Lee Metric ECC
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Solution Overview
Problem
Existing memory systems face inefficiencies in error detection and correction, particularly in multi-level cell (MLC) NAND flash memories, where conventional error correction codes (ECC) provide excessive error handling and resource utilization due to their ability to correct errors between adjacent levels, leading to unnecessary complexity and resource allocation.
Innovation Solution
The implementation of a memory system using a Lee metric code ECC system, which converts binary data into p-adic numbers and maps them to MLC levels, allowing for efficient error detection and correction by reducing the parity part size and optimizing error handling for adjacent level errors, thereby increasing the number of correctable cells while minimizing unnecessary error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC systems are used to correct errors between adjacent levels in MLC, then error correction capability is improved, but device complexity and resource allocation increase unnecessarily
Solution Approach 1:
The patent applies local quality by making the ECC system's error correction capability adaptive to the specific error patterns in MLC memories. Instead of providing uniform correction capability for all types of errors, the system is optimized to specifically handle adjacent level errors, which are the most common in MLC. This localized optimization reduces overall system complexity while maintaining high reliability for the predominant error type.
Solution Approach 2:
The patent changes the parameters of the ECC system by modifying the code structure and correction thresholds to match the statistical distribution of errors in MLC memories. By adjusting these parameters, the system achieves efficient correction of adjacent level errors without requiring the excessive complexity of conventional ECC systems designed for more general error patterns.
2Reliability
If conventional ECC systems are used to handle all error types, then error detection coverage is improved, but resource usage increases due to excessive error handling
Solution Approach 1:
The patent extracts and addresses only the most relevant error type (adjacent level errors) rather than attempting to handle all possible error types. This selective approach removes unnecessary error handling mechanisms, reducing resource usage while maintaining adequate detection coverage for the predominant error patterns in MLC memories.
3Quantity of substance
If multi-leveling is applied to increase storage capacity, then data storage density is improved, but data error rate increases
Solution Approach 1:
The patent applies beforehand cushioning by implementing an ECC system specifically optimized for MLC error characteristics before errors occur. The system is pre-configured with correction capabilities tailored to adjacent level errors, providing a cushion against the increased error rates inherent in multi-leveling without requiring excessive overhead.
Data Source
AI summary
A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly.