MLC Memory Partial-Page Compression for Faster Read Latency

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

NAND flash memory systems experience increased read latency due to the need for multiple reference voltage comparisons when switching from single level cell to multilevel cell architectures, leading to inefficiencies in data retrieval.

Innovation Solution

Implementing a read with partial page compression method that compresses data using Huffman encoding, allowing for parallel processing of sensing operations and reducing the amount of data output, thereby accelerating the read operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple reference voltage comparisons are performed in MLC memory systems, then data storage capacity is improved, but read latency increases

Engineering Contradiction:
Improvedata storage capacityVSAvoidread latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing compression encoding on the first partial page data before it is fully sensed, and simultaneously sensing the second partial page data. This overlapping of operations reduces the total read latency while maintaining the capacity benefits of MLC architecture.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuity of useful action by continuously sensing memory cell data across multiple reference voltages while simultaneously compressing previously sensed data. The compression operation continues without interruption during the sensing of subsequent partial pages, maximizing resource utilization and reducing idle time.

Inventive Principle:
Principle #20Continuity of useful action

2Loss of information

If full page data is sensed and output, then data completeness is improved, but output time and latency increase

Engineering Contradiction:
Improvedata completenessVSAvoidoutput time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent segments the full page data into multiple partial pages, each corresponding to different reference voltage comparisons. By sensing and compressing these partial pages separately and in parallel where possible, the system reduces the time required to output complete data while maintaining data completeness through recombination at the controller.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by compressing only the first partial page data immediately after sensing, while the second partial page is sensed in parallel. This selective compression of portions of the data reduces overall output time while the controller reconstructs the complete page from both partial pages.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If compression encoding is performed on all data, then data transmission efficiency is improved, but processing complexity increases

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies partial action by performing compression encoding only on the first partial page data, while the second partial page data is sensed in parallel without immediate compression. This selective approach improves transmission efficiency for the compressed portion while avoiding the complexity of compressing all data simultaneously, with the controller handling the recombination.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9858994B2Memory system with MLC memory cells and partial page compression or reduction
Publication Date: 2018.01.02 SAMSUNG ELECTRONICS CO LTD
  • US9858994B2 patent drawing
  • US9858994B2 patent drawing
  • US9858994B2 patent drawing

AI summary

A memory system includes a memory device, the memory device including a memory cell array and a compression encoder, the memory cell array including a first plurality of multi level cells (MLCs). The memory device is configured to generate a first partial page by performing one or more first sensing operations on the first plurality of MLCs using one or more first reference voltages, output the first partial page, generate a second partial page by performing a second sensing operation on the first plurality of MLCs based on a second reference voltage, the second reference voltage having a different voltage level than the one or more first reference voltages, generate a compressed second partial page by compressing the second partial page using the compression encoder, and output the compressed second partial page.