Multi-level cell memory row buffer segmentation
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Solution Overview
Problem
Multi-level phase change memory (MLC-PCM) devices face challenges with long latency and high energy consumption due to row-buffer conflicts and limited flexibility in managing least significant bits (LSBs) and most significant bits (MSBs) in coupled bit schemes, which restricts the efficiency of memory access operations.
Innovation Solution
The implementation of decoupled bit schemes and disparate/associative page buffering systems allows for independent management of LSB and MSB row buffers, reducing row-buffer conflicts and enhancing memory access efficiency by enabling flexible storage and retrieval of bits without additional hardware or significant modifications, thereby improving read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a coupled bit scheme is used to store LSBs and MSBs in the row buffer, then the row buffer can store complete memory cell data, but row buffer conflicts increase and access latency increases
Solution Approach 1:
The patent divides the row buffer into separate LSB page buffer and MSB page buffer, allowing independent storage and management of least significant bits and most significant bits. This segmentation enables the system to serve access requests for LSBs and MSBs independently, reducing row buffer conflicts and decreasing access latency while maintaining complete data integrity through the coordinated operation of both buffers.
2Device complexity
If a coupled bit scheme is used, then hardware structure is simpler, but row buffer hit rate decreases and energy consumption increases
Solution Approach 1:
The row buffer is segmented into separate LSB and MSB page buffers, which increases the row buffer hit rate by allowing independent servicing of LSB and MSB access requests. Although the buffer structure becomes more complex, the patent manages this through separate latch arrays and control logic that operate independently, thereby improving productivity without requiring excessive hardware complexity.
3Ease of operation
If LSBs and MSBs are stored together in the row buffer, then data retrieval is simplified, but queuing delay increases and access time increases
Solution Approach 1:
By separating LSB and MSB storage into distinct page buffers, the patent eliminates queuing delays that would occur if both bit types had to wait for a single buffer cycle. The independent latch arrays allow simultaneous or prioritized access to LSBs and MSBs, significantly reducing queuing delay and total access time while maintaining ease of operation through coordinated buffer management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces average access time, queuing delay, and energy consumption while increasing the row buffer hit rate, making the memory system more efficient and effective in handling multiple bit operations.
Implementation Method 1
PCM exploits a behavior of chalcogenide, where heat produced by the passage of an electric current through the chalcogenide switches this material between two states, crystalline and amorphous
Implementation Method 2
data signals from the bit lines are detected by sense amplifiers and latched (stored) in peripheral circuitry known as a row buffer
Data Source
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AI summary
A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from and write to the memory device, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.