Multi-Level Cell Memory Data Scrambling for Symmetry
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Solution Overview
Problem
Existing methods for storing data in multi-level cell memory chips face challenges in ensuring symmetry across memory levels, leading to difficulties in estimating channel statistics and high coding overhead, especially in low-latency memory applications.
Innovation Solution
A device and method that uses a scrambling unit to generate candidate scrambled sequences, calculates a cost function to determine balancing degree, and selects the most balanced sequence for storage across multiple memory chips, ensuring each level is programmed equally, with a partially-parallel guided scrambling architecture to reduce latency and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If balanced code is used to ensure each MLC level is written the same number of times, then data symmetry across memory levels is improved, but coding overhead becomes very high for small block lengths
Solution Approach 1:
The patent changes the parameter of data distribution by using scrambling sequences that modify how data is mapped to memory levels. Instead of using complex balanced codes, it applies bitwise scrambling operations with carefully selected sequences that naturally balance the distribution of data across MLC levels, thereby reducing coding overhead while maintaining data symmetry.
Solution Approach 2:
The patent employs simple scrambling sequences that can be generated and discarded easily, replacing the need for complex balanced codes. These scrambling sequences are computationally inexpensive to generate and apply, providing an efficient alternative that achieves data symmetry without the high coding overhead of traditional balanced codes.
2Productivity
If enumerative encoding and decoding is performed to ensure each level is written at least k times, then coding efficiency is improved, but error propagation occurs and decoding failures happen
Solution Approach 1:
The patent replaces the mechanical enumerative encoding/decoding process with a bitwise scrambling operation. This substitution eliminates the complex encoding/decoding machinery that causes error propagation, while maintaining coding efficiency through simple XOR-based scrambling that is inherently more reliable and easier to implement in hardware.
Solution Approach 2:
The patent uses scrambling sequences as simplified copies or approximations of complex balanced codes. Instead of implementing full enumerative encoding, it uses scrambling sequences that replicate the essential function of balancing data distribution across levels, thereby achieving similar coding efficiency without the reliability issues of complex decoding processes.
3Adaptability or versatility
If data is read from and written to memory cells in small chunks, then memory access flexibility is improved, but channel statistics estimation becomes very difficult due to data asymmetry
Solution Approach 1:
The patent applies preliminary scrambling to data before it is written to memory, ensuring that even small chunks of data are pre-balanced across MLC levels. This preliminary action of scrambling prevents data asymmetry from developing in the first place, allowing accurate channel statistics estimation to be performed on small data chunks without requiring complex post-processing or large data collection.
Data Source
AI summary
A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips.