Multi-Level Cell Memory Selective Data Programming
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Solution Overview
Problem
In multi-level cell memory systems, the varying access times for most significant bits (MSBs) and least significant bits (LSBs) lead to non-uniform memory access, which can be unacceptable in certain applications, especially when power quality is a concern and data needs to be quickly backed up to prevent loss.
Innovation Solution
Implementing a method to reprogram data from volatile memory to flash memory with multi-level cells, where MSBs are grouped for fast access pages and LSBs for slow access pages, allowing for selective access speeds based on memory commands and power quality thresholds, ensuring faster access and data backup during potential power failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell memory is used to increase data density, then storage capacity per cell improves, but access time uniformity deteriorates
Solution Approach 1:
The memory access mechanism is segmented into two independent paths: one for MSBs with fast access and one for LSBs with slow access. This allows each bit to be accessed through its own dedicated path, eliminating the sequential dependency that causes non-uniform access times while maintaining the high density provided by multi-level cells.
Solution Approach 2:
Different quality levels of access are provided for different parts of the data. MSBs receive fast access treatment while LSBs receive slow access treatment, allowing each part to be accessed according to its specific requirements. This local differentiation resolves the uniformity issue without compromising the overall high-density storage capability.
2Device complexity
If all cells in a wordline are accessed simultaneously, then memory structure simplicity is maintained, but data backup reliability deteriorates during power failures
Solution Approach 1:
The memory access system transitions from a static simultaneous access model to a dynamic selective access model. Based on real-time power quality detection, the system dynamically decides whether to access fast pages, slow pages, or both, allowing the memory controller to adapt its behavior to current power conditions and ensure reliable data backup when needed.
Solution Approach 2:
A feedback mechanism is introduced where power quality information is continuously monitored and fed back to the memory controller. This feedback enables the controller to make informed decisions about which pages to access for data backup, ensuring that critical data is reliably transferred to non-volatile memory during power failures while maintaining simple operation during normal conditions.
3Speed
If fast access pages are used for all data, then access speed improves, but power consumption increases
Solution Approach 1:
Instead of always using fast access for all data (excessive action), the system uses fast access only when necessary (partial action). By selectively accessing only the fast pages when power quality is stable and critical data needs rapid retrieval, the system achieves high performance when needed while conserving power during normal operation, avoiding the excessive energy consumption that would result from continuously using fast access paths.
Data Source
AI summary
Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells. The reprogramming comprises: copying the data from the volatile memory, and writing the copied data: (1) to the most significant bits of the multi-level cells in the flash memory while skipping the least significant bits of the multi-level cells, or (2) to the least significant bits of the multi-level cells while skipping the most significant bits.