MLC Memory Encoding and Signal Mapping for Lower Read Failures
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Solution Overview
Problem
Multi-level cell (MLC) memory devices face challenges in achieving high storage density due to increased reliability issues and read-failure rates as the number of bits stored in a single memory cell increases, limited by the voltage window which reduces the difference in threshold voltage between adjacent bits.
Innovation Solution
The implementation of an MLC memory device with an encoder that encodes data at a specific code rate to generate an encoded bit stream, applied to multiple m-bit memory cells using a signal mapping module for writing, and a signal demapping module for reading, which includes error detection and correction mechanisms to enhance storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more bits are stored in a single memory cell to increase storage density, then storage capacity increases, but reliability deteriorates and read-failure rate increases
Solution Approach 1:
The patent divides the storage system into multiple memory cells (first and second memory cells) where each cell stores a portion of the total data. Instead of storing all bits in a single cell, the data is segmented across multiple cells, reducing the complexity and error probability within each individual cell while maintaining high overall storage density.
2Quantity of substance
If the number of bits per memory cell increases, then storage capacity increases, but the threshold voltage difference between adjacent bits decreases
Solution Approach 1:
The patent segments the bit storage across multiple memory cells rather than concentrating all bits in one cell. This segmentation maintains larger threshold voltage differences within each cell, improving the precision and reliability of voltage-level discrimination while achieving high effective bits per cell through the combination of multiple cells.
Solution Approach 2:
The patent transitions from a single-dimension storage approach (one cell storing all bits) to a multi-dimensional approach (multiple cells storing distributed bits). This dimensional change allows the system to achieve high storage capacity without compromising the voltage window and threshold voltage difference within each individual cell.
3Reliability
If error correction coding is applied to improve reliability, then read-failure rate decreases, but the code rate decreases (more redundancy)
Solution Approach 1:
The patent applies segmentation by dividing data across multiple memory cells, which naturally reduces the error burden on any single cell. This segmentation works synergistically with error correction coding, allowing for effective error correction with reduced redundancy compared to correcting errors in a single high-capacity cell.
Data Source
AI summary
A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.