MLC Memory State Assignment for Program Disturb Reduction
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Solution Overview
Problem
Multilevel Cell (MLC) memory devices face challenges in programming efficiency due to the need for numerous high-voltage pulses, which increases programming time and causes 'program disturb' effects, where adjacent memory cells' data states are shifted, leading to data corruption and increased gate stress.
Innovation Solution
The method dynamically assigns memory cell states to reduce the number of cells programmed to higher threshold voltage ranges by analyzing intended programmed states and inverting lower page data bits when necessary, thereby reducing the number of programming pulses and minimizing program disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more high-voltage pulses are applied to program MLC memory cells to higher threshold voltage ranges, then more data states can be stored, but programming time increases and gate stress increases
Solution Approach 1:
The patent inverts lower page data bits before programming when the number of 0s exceeds a threshold, which reduces the number of cells that need to be programmed to higher threshold voltage ranges. This inversion strategy decreases the total number of programming pulses required, thereby reducing programming time while maintaining full data storage capacity.
Solution Approach 2:
The patent dynamically changes the programming parameters by counting the number of 0s in lower page data and conditionally inverting bits based on this count. This parameter change approach optimizes the distribution of cells across threshold voltage ranges, reducing the need for high-voltage pulses and decreasing programming time.
2Manufacturing precision
If more high-voltage pulses are applied to program MLC memory cells, then higher threshold voltage ranges can be achieved, but program disturb effects increase causing data corruption
Solution Approach 1:
By inverting lower page data bits when the count of 0s exceeds a threshold, the patent reduces the number of programming operations required. Fewer programming pulses mean reduced capacitive coupling effects and less program disturb to adjacent cells, thereby maintaining data integrity while achieving the required threshold voltage precision.
Solution Approach 2:
The patent applies preliminary inversion of data bits before programming to prevent the need for excessive high-voltage pulses. This preliminary action counteracts the potential for program disturb effects by reducing the total programming stress applied to the memory array, thus protecting adjacent cells from data corruption.
3Quantity of substance
If more high-voltage pulses are applied to MLC memory cells, then higher data states can be programmed, but gate stress increases reducing cell reliability
Solution Approach 1:
The patent dynamically adjusts programming parameters by counting 0s in lower page data and conditionally inverting bits. This parameter optimization reduces the total number of high-voltage pulses required to program all cells, thereby reducing cumulative gate stress while maintaining the ability to store multiple data states.
Solution Approach 2:
The inversion strategy reduces the proportion of cells requiring programming to higher threshold voltage ranges, which are the cells that experience the most gate stress. By inverting data strategically, the patent minimizes the number of cells subjected to multiple high-voltage pulses, preserving gate integrity while maintaining full data state capacity.
Data Source
AI summary
Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition.