MLC Memory Programming via Dynamic Vd Bias Adjustment
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Solution Overview
Problem
Conventional multi-level cell (MLC) memory programming methods result in a widened threshold voltage distribution due to faster bits being programmed again, leading to increased bit error rates.
Innovation Solution
The method involves adjusting the Vd bias by a fixed amount based on whether at least one bit passes the program verify level, reducing the bias when bits pass and increasing it when none do, to tighten the program distribution and enhance programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two steps of program operations are performed to tighten Vt distribution, then manufacturing precision is improved, but device complexity is increased
Solution Approach 1:
The patent applies dynamics by making the Vd bias adjustable rather than fixed. The bias is dynamically modified based on whether bits pass the PV level during program operations, allowing the system to adapt the programming parameters in real-time to achieve tight Vt distribution without requiring multiple fixed program steps
Solution Approach 2:
The patent changes the parameter of Vd bias during the program operation. By modifying the Vd bias value based on the passage of bits through the PV level, the system achieves tightened Vt distribution through parameter adjustment rather than through multiple discrete program steps
2Manufacturing precision
If faster bits are programmed again in the second program operation, then manufacturing precision is improved, but productivity is worsened
Solution Approach 1:
The patent implements feedback by monitoring whether bits pass the PV level during program operations. Based on this feedback, the Vd bias is adjusted to reduce over-programming of faster bits while ensuring slower bits are properly programmed, thereby maintaining precision without the need for additional program steps
Solution Approach 2:
The dynamic adjustment of Vd bias based on real-time monitoring of bit passage through PV level prevents redundant programming operations. This allows the system to achieve tight Vt distribution without repeatedly programming faster bits, thus maintaining high productivity
3Manufacturing precision
If Vd bias is reduced to program faster bits, then manufacturing precision is improved, but productivity is worsened
Solution Approach 1:
The patent makes the Vd bias dynamic by adjusting it based on the programming progress. The bias is reduced only when necessary (when bits pass PV level) and increased when needed (when no bits pass PV level), optimizing both precision and productivity through adaptive control
Solution Approach 2:
The patent changes the Vd bias parameter adaptively during programming. By modifying the bias value based on whether bits are passing the PV level, the system achieves tight program distribution without continuously reducing the bias, thereby maintaining high programming speed
Data Source
AI summary
A method for programming a MLC memory includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.