MLC Memory Error Correction Using Verification Voltage Readjustment
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Solution Overview
Problem
Multi-level cell (MLC) memory devices face increased read-failure rates due to overlapping threshold voltage distributions as the number of bits stored in a single memory cell increases, leading to errors in data retention and retrieval.
Innovation Solution
A memory device with a reading unit, error correction unit, control unit, and programming unit that detects error bits, identifies affected memory cells, applies verification voltages, and readjusts data to correct errors, thereby managing error rates and extending data retention time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in a single memory cell increases to achieve higher integration, then storage density is improved, but threshold voltage distributions overlap and read-failure rate increases
Solution Approach 1:
The patent segments the threshold voltage distribution into multiple sub-distributions by introducing intermediate verification voltages between adjacent data threshold voltages. This creates distinct reading regions that prevent overlap and misidentification of adjacent threshold voltage levels, thereby reducing read-failure rate while maintaining high storage density
Solution Approach 2:
The patent introduces intermediate verification voltages as intermediary elements between adjacent data threshold voltages. These verification voltages act as mediators to clearly distinguish between adjacent threshold voltage distributions, enabling reliable reading of multi-bit data without confusion from overlapping distributions
2Reliability
If error correction codes are used to detect and correct errors, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary reading of data at intermediate verification voltages before final data interpretation. This preliminary action allows the system to detect potential reading errors before they occur, enabling correction without requiring complex error correction codes, thus improving reliability while controlling complexity
Solution Approach 2:
The patent implements a feedback mechanism where reading operations at intermediate verification voltages provide information about the actual threshold voltage distribution. This feedback allows the system to adjust reading voltages dynamically, improving reading accuracy and data reliability without requiring complex error correction coding
Data Source
AI summary
Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.