MLC Memory Programming Tightening Vt Distribution
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Solution Overview
Problem
Conventional multi-level cell (MLC) memory programming methods require two-step programming operations, increasing program control flow overhead and resulting in a widened threshold voltage distribution and higher bit error rates due to re-programming faster bits.
Innovation Solution
A method where bits are programmed to pass a higher program verify level in the first operation, ensuring only slower bits are re-programmed to pass the initial level in the second operation, tightening the distribution and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-step program operation is used to tighten Vt distribution, then programming precision is improved, but device complexity and control flow overhead increase
Solution Approach 1:
The programming operation is divided into two distinct steps: a first program operation that programs bits to pass a higher PV level, and a second program operation that programs only bits not passing the PV level. This segmentation allows different programming strategies for different bit groups, achieving tightened Vt distribution while managing control complexity through structured division of labor.
Solution Approach 2:
The first program operation performs preliminary programming to achieve a higher PV level before the final verification. By pre-programming bits to exceed the target PV level, the system ensures that subsequent fine-tuning operations only need to address bits that failed the initial higher-level verification, thereby tightening the final Vt distribution.
2Manufacturing precision
If two-step program operation is used to tighten Vt distribution, then programming precision is improved, but bit error rate increases due to re-programming faster bits
Solution Approach 1:
The second program operation applies local quality by selectively programming only the subset of bits that did not pass the PV level in the first operation. Faster bits that already exceeded the PV level are excluded from re-programming, while only slower bits receive additional programming pulses. This localized approach prevents unnecessary re-programming of faster bits, thereby reducing bit error rates while maintaining tightened Vt distribution.
3Manufacturing precision
If bits are programmed to pass higher PV level in first operation, then Vt distribution is tightened, but programming time increases
Solution Approach 1:
The first program operation performs preliminary programming to achieve a higher PV level, which serves as a stricter intermediate target. By setting this higher bar initially, the system identifies and separates faster bits that can be excluded from subsequent operations, reducing the overall programming time despite the additional verification step.
Solution Approach 2:
The system incorporates feedback from PV level verification to control the second program operation. Only bits that failed to pass the PV level in the first operation are selected for re-programming in the second operation. This feedback-driven selection mechanism ensures that programming time is not wasted on bits that already meet the higher PV level requirement, thereby optimizing the time-performance tradeoff.
Data Source
AI summary
A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises programming the bits of the memory having a Vt level lower than the first PV level of the targeted programmed state such that at least one bit of them has a Vt level larger than a second PV level corresponding to a targeted programmed state, wherein the second PV level of the targeted programmed state is larger than the corresponding first PV level; and programming only the bits of the memory with a Vt level lower than the first PV level of the targeted programmed state such that each of them has a Vt level larger than the first PV level of the targeted programmed state.