Non-Volatile Multilevel Memory Cell Programming Method
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Solution Overview
Problem
As NAND flash memory scales, parasitic capacitance coupling between adjacent memory cell floating gates leads to wider Vt distributions, degrading programming performance, especially in multi-level cell (MLC) devices where threshold voltage differences are small, causing floating gate-to-floating gate interference and reduced reliability.
Innovation Solution
A method is introduced to program non-volatile multilevel memory cells by shifting threshold voltages to eliminate cells with negative threshold voltages, reducing floating gate-to-floating gate interference, by programming a lower page followed by an upper page, ensuring all cells have positive threshold voltages, thereby compacting and narrowing the threshold voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory is scaled down, then memory density is improved, but parasitic capacitance coupling between adjacent floating gates increases causing wider Vt distribution
Solution Approach 1:
The patent segments the programming process into multiple stages (e.g., programming even pages first, then odd pages; or programming lower pages before upper pages). This segmentation allows intermediate verification and correction steps that prevent cumulative interference effects from widening the Vt distribution, thereby maintaining manufacturing precision while enabling continued scaling for higher density.
Solution Approach 2:
The patent applies preliminary actions by programming certain pages or pages with specific characteristics first (e.g., even pages before odd pages, or cells with lower threshold voltages first). This preliminary programming establishes a baseline state that reduces subsequent interference during later programming operations, preventing Vt distribution widening while maintaining the ability to scale memory density.
2Quantity of substance
If multiple level cell (MLC) programming is implemented, then storage capacity per cell is improved, but floating gate-to-floating gate interference increases due to small threshold voltage differences
Solution Approach 1:
The patent segments MLC programming into distinct phases (e.g., programming to first threshold level, verifying, then programming to second threshold level). This segmentation allows the system to manage small threshold voltage differences in controlled steps, reducing the impact of floating gate interference while maintaining high storage capacity per cell through multilevel operation.
Solution Approach 2:
The patent incorporates verification steps that provide feedback on the actual threshold voltage achieved after programming. This feedback mechanism allows the system to detect and correct deviations caused by floating gate interference, ensuring reliable MLC programming despite the challenging small threshold voltage differences between states.
3Manufacturing precision
If threshold voltage distribution is widened due to parasitic coupling, then programming margin is reduced, but programming speed must be maintained
Solution Approach 1:
The patent employs periodic programming and verification cycles rather than continuous programming. This periodic action allows the system to pause programming, verify threshold voltage placement within acceptable margins despite parasitic coupling effects, and then continue programming. This maintains programming margin while achieving acceptable overall programming speed through efficient cycle management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces floating gate-to-floating gate interference, improves programming performance, and enhances the reliability of multi-level cell NAND arrays by maintaining tighter threshold voltage distributions and reducing verify voltage differences, leading to more accurate and efficient data storage.
Implementation Method 1
parasitic capacitance coupling between adjacent memory cell floating gates becomes a problem
Data Source
AI summary
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell to a first Vt within a lowermost Vt range. The method includes programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell. The method includes programming the upper page of the first wordline cell such that the first Vt is increased to a second Vt, wherein the second Vt is within a Vt range which is then a lowermost Vt range and is positive.