MLC MRAM Memory Subsystem for CNN AI Processing
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Solution Overview
Problem
Existing CNN-based ICs for AI face challenges with slow computational speed and high power consumption due to the impractical integration of different memory technologies and security concerns, particularly when processing large amounts of imagery data.
Innovation Solution
A CNN-based digital IC with a memory subsystem that integrates multi-level cell (MLC) magnetic random access memory (MRAM) for both weight storage and input signal storage, using either STT-RAM or OST-MRAM, allowing for low power consumption and high read/write speed, with the option for one-time-programming (OTP) memory for enhanced security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different memory technologies (SRAM and Flash) are integrated on a single silicon chip, then weight storage and input signal storage requirements are met, but manufacturing complexity increases and power consumption becomes too high
Solution Approach 1:
The patent merges weight storage and input signal storage into a single MLC MRAM memory structure. The memory device includes a first set of memory cells for weights and a second set of memory cells for input signals, both implemented using the same MLC MRAM technology on a single silicon chip, eliminating the need for heterogeneous memory integration
Solution Approach 2:
The MLC MRAM memory device is designed to serve multiple functions: storing both weights and input signals, supporting different read modes (full array read, column read, row read), and providing both volatile and non-volatile storage capabilities through the same hardware structure
2Use of energy by stationary object
If MLC MRAM is used for both weight and input signal storage, then power consumption is reduced and read/write speed is improved, but security concerns arise
Solution Approach 1:
The memory device is segmented into distinct functional regions: a first set of memory cells for weights, a second set for input signals, and a third set for security keys. This segmentation allows security-sensitive data to be isolated in dedicated cells that can be protected with unique access mechanisms
Solution Approach 2:
Different security measures are applied to different parts of the memory device. The security key storage region has enhanced protection mechanisms compared to regular data storage, allowing localized security enforcement without affecting overall system performance
3Adaptability or versatility
If MLC MRAM cells are configured for both volatile and non-volatile operation, then adaptability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes in the MLC MRAM cells to achieve different operational modes. By adjusting read voltage levels and pulse durations, the same physical memory cells can operate in volatile mode for fast access or non-volatile mode for persistent storage, without requiring different manufacturing specifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient processing of large imagery data with reduced power consumption and improved security by integrating MLC MRAM on a single silicon chip, addressing the limitations of prior art by providing a scalable and secure architecture for AI applications.
Implementation Method 1
an array of first magnetic random access memory cells for storing weights
Implementation Method 2
Both memories made of either MLC STT-RAM or MLC OST-MRAM
Data Source
AI summary
CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.