MLC NAND Flash Memory Programming via Bit Line Segmentation
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Solution Overview
Problem
Multilevel cell (MLC) NAND flash memory devices face issues with program disturb due to floating gate interference, leading to incorrect data reading and corrupted data, as the programmed threshold voltages can shift during programming operations, especially with capacitive coupling between cells.
Innovation Solution
The proposed method involves adjusting the bit line biasing to differentiate the programming potential for cells on the same word line, allowing for simultaneous completion of programming operations with reduced Vpass and program disturb, by using multiple verify points and altering the rate of threshold voltage change during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional programming operations are used on MLC NAND flash memory, then programming can be performed, but program disturb occurs due to floating gate interference causing threshold voltage shifts and data corruption
Solution Approach 1:
The patent segments the programming operation into multiple phases with different bit line biasing conditions. During the programming operation, bit lines are segmented into those connected to selected memory cells (where programming occurs) and those connected to unselected cells (where programming is inhibited). This segmentation prevents program disturb in unselected cells while maintaining programming functionality in selected cells.
Solution Approach 2:
The patent applies different bit line biasing conditions to different locations in the memory array. Selected bit lines receive different biasing than unselected bit lines, creating local quality differences that enable programming only in specific regions. This local differentiation prevents floating gate interference from affecting unselected cells while allowing programming in selected cells.
2Productivity
If programming operations are performed on MLC cells, then data can be written, but the number of programming pulses required increases operation time and complexity
Solution Approach 1:
The patent employs periodic verify operations during the programming process. Instead of continuous programming, the method uses periodic verification to check if threshold voltage has reached the target level, then adjusts or terminates programming accordingly. This periodic action reduces the total number of programming pulses required while maintaining programming effectiveness.
Solution Approach 2:
The patent implements feedback mechanisms where verify operations monitor the threshold voltage state of memory cells during programming. Based on this feedback, the control circuitry adjusts subsequent programming pulses or terminates programming when the target threshold voltage is achieved. This feedback-driven approach optimizes programming speed and reduces unnecessary programming operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of programming pulses required, minimizes data corruption, and maintains tight threshold voltage distributions, thereby enhancing the reliability and efficiency of MLC NAND memory programming.
Implementation Method 1
program disturb due to floating gate interference, leading to incorrect data reading and corrupted data, as the programmed threshold voltages can shift during programming operations, especially with capacitive coupling between cells
Data Source
AI summary
Methods of programming memory cells and control circuitry for memory arrays facilitate a reduction of program disturb. A memory cell is shifted from a first data state to a second data state if it is desired to alter a first digit of a data value of the memory cell. If it is desired to alter a second digit of the data value of the memory cell, the memory cell is shifted to a third data state if the memory cell is in the first data state and shifted to a fourth data state if the memory cell is in the second data state. The first, second, third and fourth data states correspond to respective non-overlapping ranges of threshold voltages. The threshold voltages corresponding to the fourth data state are greater than the threshold voltages corresponding to the third data state.