MLC NAND Flash ECC Segmentation for Unequal Page Error Rates
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Solution Overview
Problem
Current Multi Level Cell (MLC) NAND flash memory systems face inefficiencies due to unequal bit error rates between upper and lower pages, where the same error correction coding (ECC) is used for both, leading to over-protection for lower pages and underutilization of ECC power.
Innovation Solution
Pairing lower and upper pages, either within the same block, different flash dies, or different flash channels, to compute and apply split error correcting codes (ECC) specifically for each segment, allowing for more effective error correction and reduced error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same error correction coding (ECC) is used for both upper and lower pages, then implementation simplicity is maintained, but ECC effectiveness is reduced due to over-protection for lower pages and under-protection for upper pages
Solution Approach 1:
The patent divides the ECC protection into separate segments for upper and lower pages. Instead of applying a single unified ECC to both pages, the system computes and applies distinct ECC codes specifically tailored for each page type, allowing optimized error correction for each segment's specific error characteristics
Solution Approach 2:
The patent implements different ECC strategies for different parts of the memory system. Upper pages receive stronger ECC protection due to their higher error rates, while lower pages receive appropriate but less intensive protection. This localized quality adjustment optimizes overall system reliability without wasting resources on over-protection
2Reliability
If stronger ECC is applied to protect against higher error rates in upper pages, then error correction capability is improved, but code rate efficiency decreases due to over-protection of lower pages
Solution Approach 1:
The patent applies partial action by providing different levels of ECC protection matched to actual needs. Upper pages receive the necessary excessive protection to handle their higher error rates, while lower pages receive exactly the protection they need without excess. This prevents waste of correction resources on pages that don't require such strong protection
Solution Approach 2:
The patent changes the ECC parameters (code rate, redundancy level) based on the specific page being protected. By adjusting these parameters to match the actual error characteristics of upper versus lower pages, the system optimizes both reliability and code rate efficiency, avoiding the inefficiency of using fixed parameters for all pages
Data Source
AI summary
A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.