Multi-Level-Cell NAND Flash Programming Sequence Inversion
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Solution Overview
Problem
Traditional NAND flash memory devices require increased memory cells to store more data, which is inefficient, and existing programming and reading methods for multi-level-cell NAND flash memory devices are time-consuming.
Innovation Solution
A method that programs the most significant bits (MSBs) of memory cells first, followed by the least significant bits (LSBs), using a three-phase LSB read and a one-phase MSB read, along with a page buffer comprising latch circuits, bit line voltage supply, input, and precharge circuits to reduce programming and reading times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional programming methods program LSBs first then MSBs, then the programming process follows conventional sequence, but the programming time is increased
Solution Approach 1:
The patent inverts the conventional programming sequence by programming MSBs first and then LSBs, instead of the traditional LSBs-first approach. This reversal optimizes the programming time by reducing the total duration to approximately 1.5 milliseconds, while managing the sequence complexity through coordinated voltage control and verify operations for both bit groups
2Quantity of substance
If multi-level-cell memory is used to increase storage capacity, then the number of memory cells remains constant, but the programming and reading time increases
Solution Approach 1:
The patent segments the programming and reading operations into distinct phases for MSBs and LSBs. The programming process is divided into MSB programming followed by LSB programming, while reading is segmented into MSB reading with verify operations and LSB reading. This segmentation enables efficient time management and reduces total operation time despite the increased complexity of multi-level-cell operations
Solution Approach 2:
The patent performs preliminary verify operations during the MSB programming phase to ensure correct threshold voltage establishment before proceeding to LSB programming. This preliminary verification prevents rework and ensures that subsequent LSB programming operates on properly initialized memory cells, reducing overall programming time
3Measurement precision
If three-phase LSB read and one-phase MSB read are used, then the reading accuracy is improved, but the reading time is increased
Solution Approach 1:
The patent maintains continuous useful action by overlapping and coordinating the three-phase LSB read operations with the one-phase MSB read operation. The MSB read and verify operations are performed continuously during the LSB programming and reading phases, ensuring that no time is wasted between operations while maintaining high reading accuracy through the multi-phase verification process
Data Source
AI summary
Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.