MLC NAND Reduced Spatial Redundancy for Data Recovery

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Solution Overview

Problem

Multi-level cell (MLC) NAND flash memory systems face data corruption issues due to power interruptions during programming operations, as existing technologies lack effective methods to prevent data loss and corruption.

Innovation Solution

Implementing a reduced spatial redundancy method that mirrors non-most significant bits of data in a redundant memory array, allowing for data recovery in case of power interruptions without requiring a full mirror image, thus preserving data integrity and reducing memory space requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a full mirror image of data is stored in redundant memory array, then data integrity is improved, but memory space requirement doubles

Engineering Contradiction:

Improvedata integrityVSAvoidmemory space

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

Instead of storing a complete mirror image of all data, the patent applies partial redundancy by only mirroring the least significant bits (LSBs) of MLC page data. This partial action provides sufficient protection against power interruption while avoiding the excessive space consumption of full mirroring, achieving a balance between reliability and storage efficiency

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent applies different redundancy strategies to different parts of the data. Specifically, it provides redundancy protection for the least significant bits which are vulnerable to power interruption, while the most significant bits (MSBs) are stored without redundancy. This localized quality approach optimizes the protection space ratio

Inventive Principle:

Principle #3Local quality

2Reliability

If redundancy is added to prevent data corruption, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvedata corruption preventionVSAvoidmemory array structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the memory array into distinct functional regions: a main memory array for storing primary data and a redundant memory array for storing backup data. This segmentation allows the system to manage redundancy in a modular fashion, improving reliability while keeping the complexity manageable through clear structural separation

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

By implementing partial redundancy (mirroring only LSBs rather than full data), the patent reduces the complexity compared to full mirroring approaches. The redundant array stores only the necessary backup information, simplifying the overall device structure while maintaining effective protection against power interruption

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS9305655B2Solving MLC NAND paired page program using reduced spatial redundancy

Publication Date: 2016.04.05 VIRTIUM LLC

AI summary

Reduced spatial redundancy of lower bits data provides data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory assists in restoring the data, using less than a full back up storage.