MLC NAND Flash Error Correction via Sector Segmentation

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Solution Overview

Problem

Multi-level cell (MLC) NAND flash memory devices experience increased error rates due to higher memory density, requiring an efficient error correction scheme to maintain data integrity.

Innovation Solution

An error correction system integrated into the memory device that includes an error correction engine, ECC data storage, and a control circuit to manage memory operations, utilizing ECC check bits and block management data to correct errors during programming and read operations, with specific methods for SLC and MLC NAND flash memory configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-level cell (MLC) configuration is used to increase memory density, then storage capacity is improved, but error rates increase

Engineering Contradiction:
Improvememory densityVSAvoiderror rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the error correction process into multiple independent sectors, each with its own ECC check bits. This segmentation allows parallel error correction operations and reduces the impact of errors on overall data integrity. The page structure is divided into multiple sectors that can be processed independently during read and write operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs error correction check bit generation in advance during the write operation, before data is stored in the MLC memory cells. This preliminary action ensures that correction information is ready and can be immediately applied during read operations, reducing the time required for error correction and maintaining data integrity without delaying data access.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If error correction operations are performed to maintain data integrity, then reliability is improved, but time required for correction operations increases

Engineering Contradiction:
Improvedata integrityVSAvoiderror correction time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

ECC check bits are generated and stored during the initial write operation, before any read operations occur. This preliminary preparation of correction information eliminates the need for time-consuming error correction calculations during read operations, as the correction data is already available in the memory device.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements continuous error correction monitoring and correction during data read operations. The error correction process is integrated into the read operation flow, allowing correction to occur continuously without interrupting data access. This ensures data integrity is maintained without significant time loss.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If ECC check bits and block management data are stored in memory, then error correction capability is improved, but memory usage increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies different error correction strategies to different parts of the memory structure. ECC check bits are stored locally with each sector, allowing error correction for that specific sector without requiring additional global correction data. This localized approach minimizes the additional memory overhead while maintaining effective error correction capability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The block management data structure serves multiple functions: it stores allocation information, bad block markers, and ECC check bits. This multi-functional design reduces the need for separate dedicated storage structures, thereby minimizing the increase in memory usage while maintaining comprehensive error correction and management capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8943387B2Programming management data for a memory
Publication Date: 2015.01.27 MICRON TECHNOLOGY INC
  • US8943387B2 patent drawing
  • US8943387B2 patent drawing
  • US8943387B2 patent drawing

AI summary

Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Additional embodiments may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additional embodiments may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.