Self-Calibrated MLC NVM Cells for Threshold Voltage Variation
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Solution Overview
Problem
Conventional Multiple Level Cell (MLC) Non-Volatile Memory (NVM) technologies face limitations in resolving threshold voltage level variations among cells due to manufacturing non-uniformity and aging, which restricts the number of resolvable threshold voltage levels and leads to data retention issues.
Innovation Solution
Self-adaptive and self-calibrated methods and structures that program NVM cells into a fixed response tolerance window, using incremental gate voltages and sense circuit gain to manage threshold voltage variations, and include guard-band voltages to account for transconductance degradation and aging, allowing for recalibration of cells to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional reference cell comparison scheme with constant gate voltage is used, then the sensing process is simple, but the number of resolvable threshold voltage levels is limited due to manufacturing non-uniformity and transconductance variations
Solution Approach 1:
The patent applies dynamics by transitioning from a static constant gate voltage sensing scheme to a dynamic stepped gate voltage scheme. The gate voltage is incrementally increased through multiple steps, allowing the sensing system to dynamically probe different threshold voltage regions and resolve more levels despite manufacturing variations.
Solution Approach 2:
The patent changes the gate voltage parameter from a fixed constant value to a sequence of stepped values. By varying the gate voltage through multiple discrete steps, the system can distinguish between more threshold voltage levels, effectively increasing measurement precision through parameter modulation.
2Productivity
If memory cells undergo more write-erase cycles than reference cells, then memory cell usage increases, but transconductance degradation becomes more severe requiring additional compensation techniques
Solution Approach 1:
The patent implements feedback by continuously monitoring the drive current responses of memory cells during stepped gate voltage sensing. The sense amplifier compares actual cell responses against reference levels and uses this feedback information to dynamically adjust sensing thresholds and compensate for transconductance degradation accumulated over write-erase cycles.
Solution Approach 2:
The patent applies preliminary action by pre-characterizing the transconductance degradation behavior through stepped voltage sensing before it significantly impacts reliability. The system proactively detects early signs of degradation and adjusts sensing parameters in advance, preventing data retention issues before they occur.
3Ease of manufacture
If stepped gate voltages are used to sense drive current, then reference cell pre-trimming is not required, but guard-band voltage is needed between threshold voltage levels
Solution Approach 1:
The patent applies segmentation by dividing the threshold voltage sensing range into multiple discrete stepped voltage levels. Each step probes a specific voltage region, and the transitions between steps create natural separation zones (guard-bands) that eliminate the need for precise reference cell trimming while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the number of resolvable threshold voltage levels, enhances data retention, and ensures that NVM cells remain within specified operating ranges, even as they age, thereby improving the reliability and capacity of MLC NVM.
Implementation Method 1
Data is stored in an NVM cell by modulating the threshold voltage, Vth, of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) in the NVM through the injection of charge carriers into the charge-storage layer from the channel of the MOSFET.
Data Source
AI summary
Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates of NVM cells. The fixed response tolerance window is related to the threshold voltage tolerance window through the sense circuit gain. Properly choosing the sense circuit gain and the response window can control the threshold voltage tolerance window to a desired value. An incremental gate voltage larger than the threshold voltage tolerance window of each NVM cell will guarantee that each NVM cell will produce the correct output current (voltage) in response to applying to the control gate of the NVM cell the stepped voltage corresponding to the level of information stored in the NVM cell. As the stepped voltage applied to the gate of an NVM cell transitions from a voltage just below the threshold voltage of the NVM cell to a voltage corresponding to the threshold voltage of the NVM cell, the output current (voltage) from the NVM cell will pass the current (voltage) transition in comparison with the reference current (voltage). The current (voltage) transition can be detected and converted into the bit-word information representing the voltage level stored in the NVM cell. When the response of an NVM cell falls outside the response tolerance window into the guard-band regions, the NVM cell can be re-calibrated and the bit-word information can be saved from fading away.