Reduced-Element Page Buffer Circuit for MLC Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing page buffer circuits in Multi-Level Cell (MLC) memory devices require a large number of elements, which hinders the increase in integration density and efficiency of programming and reading operations.
Innovation Solution
A reduced-element page buffer circuit design that includes a MSB latch, LSB latch, data I/O circuit, inverted output circuit, and verification circuits, which selectively outputs and verifies data for programming and reading operations, reducing the total number of components to 18 elements from the conventional 24, while maintaining efficient data transfer and verification processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional page buffer circuits are used in MLC memory devices, then data storage capacity is maintained, but the number of elements increases and integration density decreases
Solution Approach 1:
The patent combines the MSB latch and LSB latch into a single integrated page buffer circuit structure. The MSB latch unit and LSB latch unit share common circuit elements and are controlled by unified control signals, reducing the total element count while maintaining the ability to store and manipulate both MSB and LSB data independently for MLC operations.
Solution Approach 2:
The page buffer circuit is designed to perform multiple functions using a reduced set of elements. The same latch circuits and control mechanisms are used for both MSB and LSB operations, as well as for both program and verify phases, eliminating the need for separate dedicated circuits for each function and thereby reducing overall device complexity.
2Reliability
If conventional page buffer circuits with more elements are used, then data verification capability is maintained, but integration density and programming efficiency decrease
Solution Approach 1:
The page buffer circuit performs preliminary data verification during the program operation itself. The latch circuits are designed to verify data integrity before final programming completion, allowing for early detection of programming failures and reducing the need for separate verification passes, thereby improving programming efficiency while maintaining reliability.
3Ease of operation
If conventional page buffer circuits are used, then complete data latching functionality is provided, but circuit area increases and integration density decreases
Solution Approach 1:
The LSB latch is nested within or closely integrated with the MSB latch structure. The circuit elements are arranged in a hierarchical manner where smaller functional units are embedded within larger ones, maximizing space utilization and reducing the overall circuit area while maintaining complete data latching functionality for both MSB and LSB.
Data Source
AI summary
A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data.