Page Buffer Verification Speed in Multi-Level Cell Memory
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Solution Overview
Problem
The existing non-volatile memory devices require increased time for verifying operations due to the need for multiple verifying steps in multi-level cell programming, which affects storage capacity and efficiency.
Innovation Solution
A non-volatile memory device with a page buffer that includes multiple registers and sensing node discharging circuits, allowing for independent verifying operations by coupling sensing nodes to ground based on data stored in registers, thereby reducing the time required for each verifying operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple verifying operations are performed sequentially in multi-level cell programming, then the accuracy of data verification is improved, but the total verification time increases
Solution Approach 1:
The page buffer is divided into multiple independent verifying units, each capable of performing verification operations simultaneously. Each verifying unit includes dedicated sensing nodes and discharging circuits that can operate independently, allowing parallel execution of multiple verification steps without sequential delays
Solution Approach 2:
Multiple verifying units are merged within a single page buffer structure, sharing common control logic and data pathways while maintaining independent sensing and discharging capabilities. This consolidation enables parallel verification operations within a unified architectural framework
2Reliability
If multiple verifying operations are performed sequentially, then comprehensive data verification is achieved, but the programming efficiency decreases
Solution Approach 1:
The verification process is segmented into independent verifying units that can operate simultaneously. Each unit handles specific verification tasks independently, allowing comprehensive verification coverage while maintaining high throughput through parallel execution
Solution Approach 2:
Multiple verification operations proceed continuously and simultaneously through parallel verifying units, eliminating idle time between sequential verification steps. The system maintains continuous productive action across all verification tasks without interruption or waiting
3Device complexity
If sensing nodes are shared across multiple verifying operations, then device complexity is reduced, but verification speed decreases
Solution Approach 1:
Sensing nodes are merged into verifying units where each unit has its dedicated sensing nodes. This consolidation within units enables simultaneous operation without the bottlenecks of shared resources, maintaining structural efficiency while achieving high-speed parallel verification
Data Source
AI summary
A page buffer in a non-volatile memory device for performing a program operation for a multi level cell having m bits includes first register to mth registers, a first data transmitting circuit configured to transmit data stored in a first node or a second node of the first register to a sensing node in accordance with a first data transmitting signal or a second data transmitting signal, and (m−1) sensing node discharging circuits configured to couple the sensing node to ground in accordance with data stored in a first node or a second node of each of the second to mth registers, and a first sensing node discharge signal or a second sensing node discharge signal.