MLC Parity Storage for Flash Memory Error Protection
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Solution Overview
Problem
Existing memory devices face inefficiencies in error protection, particularly in flash memory systems, where block erases are slow and frequent, disrupting data operations and reducing error correction capabilities.
Innovation Solution
Implementing multi-level memory cells (MLC) to store parity data in a way that allows multiple changes without requiring a block erase, using a parity generator array to manage parity data changes below a threshold, enabling efficient error protection without frequent block erases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block erase operations are performed frequently to maintain error correction capabilities, then error protection reliability is improved, but operational speed deteriorates and productivity decreases
Solution Approach 1:
The patent segments the memory array into multiple sub-arrays, each with its own parity data stored in dedicated MLC cells. This allows error correction to be performed independently in each sub-array without requiring a full block erase operation across the entire memory, thereby maintaining error protection while reducing the scope and frequency of erase operations.
Solution Approach 2:
The patent dynamically manages parity data by allowing multiple changes to parity bits within MLC cells before triggering a block erase. The system monitors the number of parity changes and only performs a block erase when a threshold is reached, enabling flexible adaptation between maintaining error correction capability and minimizing slow erase operations.
2Reliability
If block erase operations are performed frequently to maintain error correction capabilities, then error protection reliability is improved, but productivity deteriorates
Solution Approach 1:
By dividing the memory into sub-arrays with independent parity management, the patent enables localized error correction that does not require stopping all data operations. Only the affected sub-arrays need attention, allowing other parts of the memory to continue productive operations without interruption.
Solution Approach 2:
The dynamic threshold mechanism allows the system to accumulate multiple parity changes before performing a block erase. This reduces the frequency of productivity-disrupting erase operations while still maintaining error correction capabilities through continuous monitoring and conditional intervention.
3Reliability
If more memory is allocated for parity data to enhance error protection, then error correction capabilities are improved, but memory capacity for actual data decreases
Solution Approach 1:
The patent changes the state parameters of MLC cells from traditional SLC to MLC configuration, enabling each parity cell to store multiple parity bits through multiple programmable states. This reduces the number of physical cells needed for parity storage while maintaining or enhancing error correction capabilities, thereby preserving more memory capacity for actual data.
Solution Approach 2:
The MLC cells used for parity storage serve multiple functions: they can store multiple parity bits per cell, support dynamic reconfiguration based on error patterns, and enable more efficient error correction algorithms. This multi-functionality reduces the overall memory overhead required for error protection compared to traditional dedicated single-bit parity cells.
Data Source
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AI summary
Subject matter disclosed herein relates to methods and/or apparatuses, such as an apparatus that includes first and second groups of memory cells. The first group of memory cells stores multiple digits of program data per memory cell. The second group of memory cells stores a parity symbol per memory cell. Other apparatuses and/or methods are disclosed.