Multi-level Phase-change Memory Device Programming
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Solution Overview
Problem
Multi-level cell (MLC) nonvolatile memory devices face challenges in improving the speed and reliability of read and program operations due to increased time and power requirements when storing multiple bits per memory cell.
Innovation Solution
The implementation of an MLC phase-change memory device that divides data into groups and uses a write driver to generate pulse currents with specific characteristics (magnitude, slope, or duration) to program phase-change memory cells, and a sensing block to identify data by comparing bit line voltages with reference voltages, allowing for efficient storage and retrieval of multiple bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits of data are stored in each memory cell to improve storage capacity, then storage capacity is improved, but read and program operation time increases
Solution Approach 1:
The patent divides data into multiple data groups (first data group, second data group, etc.), each corresponding to different bit positions within a multi-bit memory cell. This segmentation allows the system to process and program different portions of multi-bit data separately, reducing the overall programming time compared to programming all bits simultaneously.
Solution Approach 2:
The patent employs periodic pulse current actions with different characteristics (first pulse current, second pulse current, third pulse current) to program different data groups. Each pulse current has specific characteristics (magnitude, duration, slope) tailored to program specific bit combinations, enabling efficient multi-level cell programming through repeated periodic operations.
2Quantity of substance
If multiple bits of data are stored in each memory cell to improve storage capacity, then storage capacity is improved, but power consumption increases
Solution Approach 1:
The patent changes pulse current parameters (magnitude, duration, slope) to optimize power consumption for different programming scenarios. By using pulse currents with different characteristics for different data groups, the system consumes only the necessary power for each specific programming operation, reducing overall power consumption compared to using a single high-power pulse for all bits.
Solution Approach 2:
The patent applies partial programming actions by using different pulse currents for different data groups. Instead of applying maximum power to program all bits simultaneously, the system applies partial programming actions with appropriate pulse characteristics for each data group, reducing excessive power consumption while achieving the desired storage capacity.
3Quantity of substance
If multiple bits of data are stored in each memory cell to improve storage capacity, then storage capacity is improved, but operation reliability decreases
Solution Approach 1:
The patent segments multi-bit data into separate data groups and programs them using different pulse current characteristics. This segmentation reduces interference between bits during programming and reading operations, improving reliability. Each data group can be independently verified and corrected, enhancing overall operation reliability for multi-bit memory cells.
Solution Approach 2:
The patent implements sensing operations that read back programmed data to verify correctness. The sensing block detects the resistance state of memory cells after programming and compares it with expected values, providing feedback to detect and correct programming errors. This feedback mechanism significantly improves the reliability of read and program operations in multi-level cell memory.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the speed of read and program operations in MLC phase-change memory devices, reduces power consumption, and improves data storage capacity by enabling the storage of multiple bits with a single pulse current and read operation.
Implementation Method 1
a phase-change memory cell array comprising a plurality of phase-change memory cells each configured to store multiple bits of data using variable resistance characteristics of a phase change material
Implementation Method 2
generating a pulse current with a pulse current characteristic corresponding to a data value of one of the data groups, and to output the pulse current to a selected phase-change memory cell
Data Source
AI summary
A multi-level cell (MLC) phase-change memory device divides data into data groups each comprising multiple bits of data, and stores each of the data groups in a selected phase-change memory cell. A data group is stored in a selected phase-change memory cell by applying a pulse current to the selected phase-change memory cell with a pulse current characteristic corresponding to a data value of the data group. The pulse current characteristic can comprise, for instance, a magnitude, downward slope, or duration of the pulse current. Data is read from a selected phase-change memory cell by sensing a voltage of a bitline connected to the selected phase-change memory cell and comparing the sensed voltage simultaneously with a plurality of reference voltages.