Multi-Level Cell Programming Using Segmented Verify Voltages
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Solution Overview
Problem
Incremental step pulse programming (ISPP) methods for multi-level cell (MLC) nonvolatile memory devices require a large number of program pulses and increased programming time due to the need for small voltage increments to maintain a sufficient read margin, which slows down the operation of MLC devices.
Innovation Solution
A two-step verify operation is implemented during the programming process, where the memory cells are divided into three regions based on threshold voltage ranges using different verify voltages, allowing for faster programming by applying different program voltages to bitlines connected to memory cells in each region, and using a constant verify voltage to reduce the number of pre-charge operations and sense times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If incremental step pulse programming is used with small voltage increments to maintain sufficient read margin, then the read margin is improved, but the number of program pulses and programming time increase
Solution Approach 1:
The patent segments the memory cells into three distinct regions (first region with threshold voltage below first verify voltage, second region with threshold voltage between first and second verify voltages, third region with threshold voltage above second verify voltage) based on their threshold voltage distributions. This segmentation allows different program voltages to be applied to different regions, enabling faster programming while maintaining read margin through targeted programming of each region.
Solution Approach 2:
The patent applies local quality by assigning different program voltages to different regions of memory cells based on their threshold voltage characteristics. The first region receives a first program voltage, the second region receives a second program voltage, and the third region receives a third program voltage. This localized approach optimizes programming speed for each region while ensuring overall read margin is maintained.
2Productivity
If a constant verify voltage is applied during verify operation, then the number of pre-charge operations and sense times is reduced, but the ability to distinguish memory cell regions must be maintained
Solution Approach 1:
The patent introduces dynamics by applying verify voltages at different levels (first verify voltage and second verify voltage) at different stages of the programming process. The first verify voltage is applied after initial programming to identify cells for the first region, and the second verify voltage is applied later to identify cells for the third region. This dynamic verification approach enables accurate region distinction while maintaining programming speed.
Solution Approach 2:
The patent applies skipping by using the verify operation to rapidly identify and categorize memory cells into different regions based on their threshold voltage responses to verify voltages. This allows the system to skip unnecessary programming iterations for already-categorized cells and focus programming efforts only on cells that need adjustment, thereby accelerating the overall programming process while maintaining precision.
Data Source
AI summary
A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.