Sector Spreading MLC Memory Bit Encoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-level cell (MLC) memory devices require a large number of reference voltages to read data, which increases as more bits are stored in each cell, leading to reduced voltage differences and higher likelihood of bit jumping errors, making it inefficient and prone to errors.
Innovation Solution
Data is stored across pairs of memory cells, with each bit being partially stored in both cells, allowing for reading with fewer reference voltages and using error correction codes to select the correct constellation, reducing the average number of references needed per sector.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more bits are stored in each MLC memory cell, then storage capacity is improved, but the number of reference voltages needed to read data increases and voltage differences between bit values decrease
Solution Approach 1:
The patent divides the data storage and reading process into segments by using multiple memory cells per sector. Each sector contains multiple memory cells that collectively store a super-symbol, allowing the system to read data with fewer reference voltages by combining information from multiple cells rather than requiring many reference voltages for a single high-capacity cell
Solution Approach 2:
The patent transitions from storing bits in a single dimension (one cell per bit) to a multi-dimensional arrangement where multiple memory cells work together to store and represent a single super-symbol. This dimensional change allows the system to reduce the number of reference voltages needed by distributing the information across multiple cells in a sector
2Quantity of substance
If more bits are stored in each MLC memory cell, then storage capacity is improved, but the likelihood of bit jumping errors increases due to reduced voltage differences
Solution Approach 1:
The patent merges multiple memory cells into a sector that collectively stores a super-symbol. By combining the readings from multiple cells and using majority voting or other combination logic, the system can correct bit jumping errors that occur in individual cells, thereby improving reliability while maintaining high storage capacity
Solution Approach 2:
The patent incorporates error correction mechanisms in advance by designing the sector structure with multiple cells that provide redundant information. This beforehand cushioning allows the system to detect and correct bit jumping errors before they affect data integrity, improving reliability without sacrificing storage capacity
3Productivity
If traditional MLC reading methods are used, then data can be read from memory cells, but the average number of references per sector is high (1.5 or more)
Solution Approach 1:
The patent segments the memory into sectors with multiple cells, where each sector collectively stores a super-symbol. This segmentation allows the reading operation to use fewer reference voltages per sector by distributing the reading burden across multiple cells rather than requiring many references for a single cell
Solution Approach 2:
The patent creates a universal sector structure that can store different super-symbols using the same multi-cell arrangement. This multi-functional design allows the same sector structure to handle various data patterns efficiently, reducing the average number of references needed per sector while maintaining reading capability for all data types
Data Source
AI summary
A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.