MLC SRAM Cell Multiplication via Current Summation
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Solution Overview
Problem
Conventional SRAM data arrays require time-consuming and power-intensive processes to perform matrix multiplication operations, as they need to sense data and transfer it to separate multiplication circuits, which is inefficient in terms of time, area, and power consumption.
Innovation Solution
The introduction of multi-level cell (MLC) SRAM cells that can perform multiplication operations directly by storing binary data values as operands and using a read bit line voltage as an operand, allowing for the combination of currents to represent the product on a current sum line, eliminating the need for separate multiplication circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional SRAM data arrays are used to store data for matrix multiplication, then data storage capability is provided, but separate multiplication circuits are required which increase device complexity and consume additional area
Solution Approach 1:
The patent merges the storage function and multiplication function into a single SRAM bit cell structure. The bit cell simultaneously stores data values and performs multiplication operations by utilizing the stored values as one operand and an input voltage as the other operand, eliminating the need for separate multiplication circuits and reducing overall device complexity and chip area.
Solution Approach 2:
The SRAM bit cell is designed to serve multiple functions: it acts as both a data storage element and a multiplication processing element. By configuring the bit cell to perform multiplication using its stored data and an external voltage operand, the structure achieves multi-functionality, reducing the need for dedicated separate circuits.
2Productivity
If data is sensed and transferred to separate multiplication circuits in conventional systems, then multiplication operations can be performed, but time is consumed for data transfer and processing
Solution Approach 1:
The storage and multiplication operations are merged into the same SRAM bit cell, eliminating the data transfer step between separate storage and processing circuits. The multiplication is performed in-place using the stored data and an input voltage, significantly reducing the time required for operation execution.
3Power
If conventional SRAM systems use separate multiplication circuits, then multiplication functionality is achieved, but power consumption increases due to additional circuitry and data transfer
Solution Approach 1:
By combining storage and multiplication functions in the SRAM bit cell, the patent eliminates the need for separate multiplication circuits and data transfer pathways, thereby reducing power consumption associated with additional circuitry and data movement while simplifying the overall circuit architecture.
4Adaptability or versatility
If conventional SRAM bit cells store single binary values, then simple storage is achieved, but the ability to perform multiplication operations directly is lost
Solution Approach 1:
The SRAM bit cell is enhanced to provide both storage and computational capabilities. By configuring the bit cell to utilize its stored binary value as one operand and an input voltage as the other operand in a multiplication operation, the structure achieves versatility without significantly increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables matrix multiplication with reduced time, area, and power consumption compared to conventional systems, as multiple MLC SRAM cells can perform operations independently without the need for additional circuitry.
Implementation Method 1
combining currents on a current sum line such that a magnitude of a total current on the current sum line is an analog representation of the multiple-bit product
Data Source
AI summary
Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations are disclosed. In one aspect, an MLC SRAM cell includes SRAM bit cells, wherein data values stored in SRAM bit cells correspond to a multiple-bit value stored in the MLC SRAM cell that serves as first operand in multiplication operation. Voltage applied to read bit line is applied to each SRAM bit cell, wherein the voltage is an analog representation of a multiple-bit value that serves as a second operand in the multiplication operation. For each SRAM bit cell, if a particular binary data value is stored, a current correlating to the voltage of the read bit line is added to a current sum line. A magnitude of current on the current sum line is an analog representation of a multiple-bit product of the first operand multiplied by the second operand.