Multi-Level Cell Solid-State Storage Reliability via Reduced Programming States
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Solution Overview
Problem
Conventional flash memory devices using multi-level cell (MLC) memory elements face reduced longevity and accuracy due to increased capacity, which is a deterrent despite the benefits of higher storage capacity, whereas single-level cell (SLC) memory elements offer better accuracy and longevity but at a higher cost.
Innovation Solution
Implementing a reduced-level cell (RLC) mode within MLC memory devices, where each MLC memory element is programmed to a subset of states, specifically using the most significant bit (MSB) states to represent data, thereby reducing the number of programming states and extending the device's longevity while maintaining lower costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell (MLC) memory elements are used to store multiple bits of data, then storage capacity increases, but accuracy and longevity decrease
Solution Approach 1:
The patent segments the MLC memory element's programming states into two distinct modes: MLC mode for high-capacity storage and SLC mode for high-reliability storage. This segmentation allows the system to divide the storage space into different functional regions, with some areas optimized for capacity and others for reliability, thereby resolving the contradiction between storage capacity and reliability
Solution Approach 2:
The patent implements dynamic mode switching capability that allows the memory device to transition between MLC mode and SLC mode based on real-time requirements. The controller can dynamically select which mode to use for different data storage operations, enabling the system to adapt between capacity-optimized and reliability-optimized states, thus resolving the fixed contradiction between capacity and reliability
2Reliability
If single-level cell (SLC) memory elements are used, then accuracy and longevity improve, but manufacturing cost increases
Solution Approach 1:
The patent makes the MLC memory device universal by enabling it to function in multiple modes (MLC mode and SLC mode). The same physical MLC memory elements can be used for both high-capacity storage and high-reliability storage depending on the selected mode, eliminating the need for separate SLC memory devices and thereby reducing manufacturing costs while maintaining the ability to achieve SLC-level reliability when needed
3Quantity of substance
If MLC memory elements are programmed to multiple states, then storage capacity increases, but the number of accurate write operations decreases
Solution Approach 1:
The patent segments the operational states of MLC memory elements into MLC mode with multiple programming states for high capacity and SLC mode with limited programming states for high durability. By segmenting the state space, the system can choose to operate in SLC mode when longevity is prioritized, thereby resolving the contradiction between capacity and write endurance
Solution Approach 2:
The patent changes the operational parameters of the MLC memory elements by adjusting the number of programming states used. In SLC mode, the system restricts programming to fewer states with larger voltage margins, which increases the number of accurate write operations the memory can endure, while in MLC mode, more states are utilized for higher capacity
Data Source
AI summary
A controller is used for an electronic memory device which has multi-level cell (MLC) memory elements. The individual MLC memory elements are capable of storing at least two bits. The controller includes a physical interface to couple the controller to the electronic memory device. The controller also includes a processing unit coupled to the physical interface. The processing unit operates the electronic memory device using a restricted number of programming states for a single data bit. The restricted number of programming states includes first and second states used to represent a most significant bit (MSB) of the at least two bits of data of the designated programming states.