Multi-Level Cell Trapping DRAM for High Density
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Solution Overview
Problem
Conventional DRAM designs face challenges in increasing density due to size limitations of storage capacitors, requiring more complex fabrication processes and being unsuitable for high-speed applications, while also needing to store multiple bits per memory cell.
Innovation Solution
A multi-level-cell trapping dynamic random access memory device is developed, featuring a charge storage layer that traps charge carriers to set or reset a threshold voltage to multiple levels, allowing for storage of multiple bits per cell using a simplified fabrication process and faster programming and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar or stacked capacitor DRAM structures are used, then data storage capability is maintained, but memory cell area increases and density cannot be increased
Solution Approach 1:
The patent extracts the charge storage function from a physical capacitor structure and relocates it to a charge storage layer formed within the semiconductor substrate. This eliminates the need for separate capacitor components, thereby reducing memory cell area while maintaining data storage capability.
Solution Approach 2:
The patent transitions from planar capacitor structures to a vertical charge storage layer configuration within the substrate. By utilizing the vertical dimension and forming charge storage layers at different depths, the design achieves higher density without increasing lateral cell area.
2Area of stationary object
If capacitorless SOI trapping DRAM is used to reduce space, then fabrication process complexity increases
Solution Approach 1:
The patent uses the semiconductor substrate itself to provide charge storage functionality through implanted charge storage layers. The substrate serves dual purposes: as the structural foundation and as the charge storage medium, eliminating the need for complex external capacitor structures and simplifying the overall fabrication process.
3Productivity
If conventional DRAM designs are used, then fabrication process is established, but programming and erasing speed is slow
Solution Approach 1:
The patent pre-forms charge storage layers within the substrate during the semiconductor manufacturing process. This preliminary preparation of charge storage regions enables faster programming and erasing operations, as the infrastructure for charge storage is already in place rather than requiring complex real-time capacitor charging/discharging cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a more compact memory cell structure with higher bit density, simplified fabrication, and faster response times for programming and erasing, addressing the limitations of conventional DRAM designs.
Implementation Method 1
a charge storage layer that traps charge carriers to set or reset a threshold voltage to multiple levels
Data Source
AI summary
A memory device having at least one multi-level memory cell is disclosed, and each multi-level memory cell configured to store n multiple bits, where n is an integer, wherein the multiple bits are stored in a charge storage layer trapping charge carriers injected by application of a voltage to set or reset a threshold voltage Vt of the memory cell to one of 2n levels. Each memory cell may be programmed to one of 2n multiple levels, wherein each level represents n multiple bits.