Multi-Level Cell Writing with Double Encoding Error Correction
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Solution Overview
Problem
Writing operations in multi-level cell storage devices often result in increased error likelihood, leading to uncorrectable errors that consume computing resources and increase latency due to on-chip data copying and re-sending.
Innovation Solution
Implementing on-chip data copying with double encoding using low-density parity check (LDPC) and Bose–Chaudhuri–Hocquenghem (BCH) error correction codes to correct errors before writing data to higher cell-order blocks, reducing the likelihood of errors and conserving computing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written directly to higher cell-order blocks (MLC, TLC, QLC), then storage capacity and efficiency are improved, but error likelihood increases leading to uncorrectable errors
Solution Approach 1:
The patent segments the writing process into two distinct phases: first writing to lower cell-order blocks (SLC) as an intermediate step, then copying to higher cell-order blocks (MLC/TLC/QLC). This segmentation allows error correction to be applied at the intermediate SLC stage before final storage, resolving the contradiction between storage efficiency and error rate.
Solution Approach 2:
The patent performs preliminary error correction by writing data to SLC blocks first, applying error correction codes during this intermediate stage. This preliminary action ensures that errors are corrected before the data is finally written to higher cell-order blocks, maintaining reliability while achieving storage efficiency.
2Adaptability or versatility
If on-chip data copying is performed from lower to higher cell-order blocks, then storage flexibility is improved, but computing resources are consumed and latency increases
Solution Approach 1:
The patent implements self-service by performing the copying operation within the storage device itself (on-chip copying from SLC to MLC/TLC/QLC blocks) rather than requiring external host intervention. This eliminates the need for data to leave and re-enter the device, reducing latency while maintaining storage flexibility.
Solution Approach 2:
The patent merges the error correction process with the copying process by performing both operations in sequence within the storage device. The error correction during the SLC writing phase and the subsequent on-chip copying are combined into a unified workflow, improving efficiency and reducing overall latency.
3Device complexity
If on-chip data copying is performed without error correction, then device complexity is reduced, but uncorrectable errors increase consuming computing resources
Solution Approach 1:
The patent applies local quality by implementing error correction specifically at the intermediate SLC block stage, where it is most effective. Rather than applying complex error correction to all blocks uniformly, the system targets the critical intermediate storage phase, maintaining reliability while controlling overall device complexity.
Data Source
AI summary
In some implementations, a storage device may receive data for storage with a first cell order on a storage medium. The storage device may encode the data with a first encoding to generate single-encoded data. The storage device may encode the single-encoded data with a second encoding to generated double-encoded data. The storage device may write the double-encoded data, having a second cell order that is lower than the first cell order, to one or more first blocks of the storage medium. The storage device may read the double-encoded data at the storage medium. The storage device may perform decoding, associated with the second encoding, on the double-encoded data at the storage medium to generate error-corrected single-encoded data. The storage device may write the error-corrected single-encoded data, having the first cell order, to one or more second blocks of the storage medium.