Multilayer Ceramic Capacitor Asymmetric Cover Layer Noise Reduction
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Solution Overview
Problem
Multilayer ceramic capacitors generate acoustic noise due to vibrations caused by piezoelectric phenomena, and thickening the lower cover layer to reduce noise can lead to faults like cracks or delamination during the sintering process.
Innovation Solution
A multilayer ceramic capacitor design with a ceramic body having dielectric layers of 0.2 to 2.0 μm thickness, an active layer with internal electrodes, and a thicker lower cover layer than upper cover layer, where the bottommost internal electrode has an oxide layer, and specific dimensional ratios are maintained to control deformation and reduce acoustic noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the lower cover layer is thickened to reduce acoustic noise, then acoustic noise is reduced, but cracks or delamination occur during sintering process
Solution Approach 1:
The patent applies parameter changes by precisely controlling the thickness of the lower cover layer within a specific range (0.6-1.5 times the upper cover layer thickness) and controlling the oxide layer thickness on internal electrodes within specific ratios (50%≤Lo/Le×100≤80% and 30%≤to/te×100≤80%). These parameter optimizations allow the lower cover layer to be sufficiently thick to reduce acoustic noise while preventing excessive thickness that would cause cracks or delamination during sintering.
Solution Approach 2:
The patent employs composite materials by forming an oxide layer on the internal electrodes and using specific conductive paste compositions. The oxide layer acts as a protective composite structure that prevents direct exposure of internal electrodes, reducing stress concentration points that would lead to cracks. The conductive paste with specific material composition ensures proper adhesion between layers, preventing delamination while maintaining electrical conductivity.
2Quantity of substance
If the number of laminations is increased or dielectric layer is thinned to implement high capacitance, then capacitance is increased, but cracks or delamination occur during sintering process
Solution Approach 1:
The patent resolves this contradiction through parameter changes by controlling the dielectric layer thickness within a specific range (0.1-2.0 μm) and optimizing the number of laminations. This precise parameter control allows achieving high capacitance through increased laminations and thinned dielectric layers while the optimized lower cover layer thickness and oxide layer formation prevent cracks and delamination that would normally occur with such structural modifications.
Solution Approach 2:
The patent applies segmentation by dividing the capacitor structure into multiple thin dielectric layers (0.1-2.0 μm each) with internal electrodes positioned at specific intervals. This segmentation approach allows achieving high capacitance through increased number of laminations while the oxide layer on internal electrodes and optimized cover layer thickness distribute and reduce stress concentration, preventing cracks during sintering.
3Object-affected harmful factors
If the lower cover layer is made thicker than the upper cover layer to reduce acoustic noise, then acoustic noise is reduced, but the structure becomes more complex
Solution Approach 1:
The patent applies asymmetry by making the lower cover layer thickness different from the upper cover layer thickness, specifically setting the lower cover layer to be 0.6-1.5 times the thickness of the upper cover layer. This asymmetric design effectively reduces acoustic noise by providing better damping at the lower surface where vibrations are generated, while maintaining relatively simple manufacturing processes and avoiding excessive structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces acoustic noise while maintaining high capacitance and reliability by controlling the dimensions of the internal electrodes and oxide layers, preventing cracks and delamination, and ensuring efficient assembly and reduced defect rates.
Implementation Method 1
a bottommost internal electrode adjacent to the lower cover layer has an oxide layer formed on at least one of top and bottom surfaces thereof
Implementation Method 2
Since the dielectric layers have piezoelectric properties and electrostrictive properties, a piezoelectric phenomenon may occur and thus cause vibrations among the internal electrodes when alternating current (AC) or direct current (DC) voltage is applied to the multilayer ceramic capacitor
Implementation Method 3
Since the dielectric layers have piezoelectric properties and electrostrictive properties, a piezoelectric phenomenon may occur and thus cause vibrations among the internal electrodes
Data Source
AI summary
A multilayer ceramic capacitor includes: a ceramic body having laminated dielectric layers having an average thickness of 0.2-2.0 μm; an active layer including first and second internal electrodes alternately exposed through end surfaces of the ceramic body having the dielectric layer interposed therebetween and contributing to capacitance formation; upper and lower cover layers respectively formed above and below the active layer, the lower cover layer being thicker than the upper cover layer; first and second external electrodes covering the end surfaces of the ceramic body, wherein a bottommost internal electrode adjacent to the lower cover layer has an oxide layer formed on at least one of top and bottom surfaces thereof, and when lengths and thicknesses of the bottommost internal electrode and the oxide layer are denoted by ‘Le,’‘te’ and ‘Lo,’‘to’, respectively, in a cross section of the ceramic body taken in length-thickness direction, 50%<Lo/Le×100 and 30%<to/te×100<80% are satisfied.