Multilayer Ceramic Capacitor Asymmetric Cover Layer Design
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Solution Overview
Problem
Multilayer ceramic capacitors generate acoustic noise due to vibrations and are prone to mounting defects and chipping defects, particularly when the lower cover layer is thick, leading to instability and reliability issues.
Innovation Solution
A multilayer ceramic capacitor design with a ceramic body having dielectric layers of 0.2 μm to 2.0 μm thickness, an active layer with internal electrodes, and cover layers where the radius of curvature of edges is between 0.1 to 0.7 times the thickness of the upper cover layer, and specific thickness ratios of cover layers to the ceramic body, which reduces acoustic noise and prevents toppling and chipping defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the lower cover layer thickness is increased to decrease acoustic noise, then acoustic noise is reduced, but mounting defects occur frequently due to toppling over
Solution Approach 1:
The patent applies asymmetry by making the lower cover layer thicker than the upper cover layer. This asymmetric structure shifts the center of gravity downward, preventing the capacitor from toppling over during mounting while maintaining the increased lower cover layer thickness needed for acoustic noise reduction. The specific configuration is that the lower cover layer thickness is greater than the upper cover layer thickness, creating an unstable-to-stable transition in mounting behavior.
Solution Approach 2:
The patent addresses the mounting stability issue by transitioning from a two-dimensional thickness parameter to a three-dimensional geometric configuration. By specifying that the lower cover layer thickness exceeds the upper cover layer thickness, the invention adds a dimensional relationship between the two cover layers, transforming the mounting behavior from unstable to stable while maintaining acoustic noise reduction benefits.
2Object-affected harmful factors
If the polishing process is excessively or insufficiently performed on the edges and corners of the ceramic body, then chipping defects are prevented, but reliability is affected
Solution Approach 1:
The patent applies parameter changes by precisely controlling the polishing amount of the ceramic body edges and corners. The invention specifies that edges and corners are polished by a controlled amount to remove sharp protrusions that cause chipping defects during stacking, while maintaining sufficient structural integrity. This optimized polishing parameter achieves both chipping defect prevention and reliability maintenance.
Solution Approach 2:
The patent implements a standardized polishing procedure that can be replicated across production. By establishing specific polishing parameters and procedures for the ceramic body edges and corners, the invention creates a reproducible process that consistently prevents chipping defects without compromising reliability, allowing the solution to be copied across manufacturing batches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces acoustic noise to less than 20 dB, prevents chipping and mounting defects, and maintains high capacitance, ensuring improved reliability and assembly characteristics.
Implementation Method 1
Since the dielectric layers have piezoelectric and electrostrictive properties, when direct current (DC) or alternating current (AC) voltage is applied to the multilayer ceramic capacitor, a piezoelectric phenomenon occurs between the internal electrodes, causing vibrations.
Implementation Method 2
Since the dielectric layers have piezoelectric and electrostrictive properties, when direct current (DC) or alternating current (AC) voltage is applied to the multilayer ceramic capacitor, a piezoelectric phenomenon occurs between the internal electrodes, causing vibrations.
Data Source
AI summary
A multilayer ceramic capacitor may include: a ceramic body in which dielectric layers having an average thickness of 0.2 μm to 2.0 μm are stacked; an active layer configured to form capacitance by including first and second internal electrodes alternately exposed to both end surfaces of the ceramic body, having at least one of the dielectric layers interposed therebetween; an upper cover layer formed on the active layer; a lower cover layer formed below the active layer and being thicker than the upper cover layer; and first and second external electrodes covering the end surfaces of the ceramic body. At least one edge of the ceramic body in length, width, and thickness directions may be rounded. When a radius of curvature of the edge is defined as R and a thickness of the upper cover layer is defined as D, R/D may be in a range of 0.1 to 0.7.