Multilayer Ceramic Capacitor Asymmetric Electrode Margin Design
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Solution Overview
Problem
Multilayer ceramic capacitors experience deterioration in electric field characteristics due to cross talk and fringing field effects, especially when integrated chips are used, leading to weakened electric field characteristics and noise from unwanted electric field signals.
Innovation Solution
The design incorporates internal electrodes of different sizes with specific margin ratios to reduce cross talk and fringing field effects, using a dielectric layer and external electrodes to minimize the impact of unwanted electric field signals, with margin ratios of 0.33 or more in the longitudinal or width direction to effectively compensate for fringing effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the electromagnetic distance of each layer is reduced to integrate components, then the device size is reduced, but cross talk phenomenon occurs and electric field characteristics deteriorate
Solution Approach 1:
The patent applies asymmetry by configuring internal electrodes with different widths in different layers. Specifically, odd-numbered internal electrodes have a first width while even-numbered internal electrodes have a second width that is different from the first width. This asymmetric configuration disrupts the symmetric electromagnetic field distribution that causes cross talk, thereby reducing electromagnetic interference while maintaining compact device dimensions.
2Device complexity
If a single integrated chip is used, then device complexity is reduced, but electric field characteristics are weakened due to cross talk
Solution Approach 1:
The patent resolves this contradiction by implementing asymmetric electrode width configuration within the integrated chip structure. The internal electrodes alternately have different widths (first width for odd layers, second width for even layers), which creates asymmetric electromagnetic field distribution that suppresses cross talk phenomena. This allows the single integrated chip to maintain both low complexity and strong electric field characteristics.
3Quantity of substance
If internal electrodes are positioned closer together, then capacitance density is increased, but fringing field effects strengthen and cause noise
Solution Approach 1:
The patent addresses this contradiction by using asymmetric electrode width configuration. The alternating widths of internal electrodes in different layers create an asymmetric field distribution that confines the electric field more effectively between adjacent electrodes. This reduces fringing field effects that extend to adjacent components, thereby lowering noise while maintaining high capacitance density through close electrode positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces cross talk and fringing field impacts, preventing deterioration of electric field characteristics and noise, as demonstrated by the reduction in S21-parameter levels, thereby enhancing the performance of multilayer ceramic capacitors.
Implementation Method 1
A main role of such a multilayer ceramic capacitor is to accumulate charges in electrodes, to block direct current (DC) signals, and to pass alternating current (AC) signals
Implementation Method 2
such a multilayer ceramic capacitor can be seen to play a role in stabilizing an operation of an IC by bypassing and removing AC noise from a power line
Data Source
AI summary
A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes having different sizes to each other, and having first and second surfaces of the first and second internal electrodes, opposing each other in a stacking direction, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces, and opposing each other; and first and second external electrodes. When a margin of the first internal electrode in a longitudinal direction is b, and a margin of the first internal electrode in a width direction is d, a margin of the second internal electrode in a longitudinal direction is a, and a margin of the second internal electrode in a width direction is c, a ratio (a/b) of the margin (a) of the second internal electrode in the longitudinal direction to the margin (b) of the first internal electrode in the longitudinal direction is 0.33 or more (where, a>0 and b>0) or a ratio (c/d) of the margin (c) of the second internal electrode in the width direction to the margin (d) of the first internal electrode in the width direction is 0.33 or more (where, c>0 and d>0).