Multilayer Ceramic Capacitor Asymmetric Electrode Design
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Solution Overview
Problem
Multilayer ceramic capacitors often experience defects such as short circuits and high voltage stress due to steps generated during compression, where internal electrodes are not fully formed, leading to thinner edge portions and increased risk of defects during voltage testing.
Innovation Solution
The capacitors are designed with first and second internal electrodes having different body portions and lead portions exposed on the mounting surface, with external electrodes connected to these lead portions, allowing for a controlled distribution of current and reducing the step formation by varying the size difference between internal electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked dielectric layers and internal electrodes is increased to achieve higher capacitance, then the capacitance increases, but the probability of step generation in margin portions increases
Solution Approach 1:
The patent applies local quality by making the internal electrodes have different widths at different locations. Specifically, the internal electrodes have a first width in the overlapping region and a second width in the margin portion, with the second width being smaller than the first width. This local variation in electrode geometry prevents step generation in margin portions while maintaining high capacitance through increased stacking density in the overlapping region.
2Quantity of substance
If the multilayer body is compressed to improve density, then the capacitance increases, but steps are generated in margin portions where internal electrodes are not formed
Solution Approach 1:
The patent applies local quality by making the internal electrodes have different widths at different locations. Specifically, the internal electrodes have a first width in the overlapping region and a second width in the margin portion, with the second width being smaller than the first width. This local variation in electrode geometry prevents step generation in margin portions while maintaining high capacitance through increased stacking density in the overlapping region.
Solution Approach 2:
The patent applies asymmetry by designing internal electrodes with non-uniform width along the stacking direction. The electrodes are wider in the overlapping region and narrower in the margin portions, creating an asymmetric geometry that prevents step formation during compression while maintaining effective capacitance through optimized overlapping area.
3Shape
If the multilayer body is compressed, then the internal electrodes bend to fill empty space, but the thickness of edge portions becomes thinner, causing short circuits and high voltage stress defects
Solution Approach 1:
The patent applies local quality by making the internal electrodes have different widths at different locations. Specifically, the internal electrodes have a first width in the overlapping region and a second width in the margin portion, with the second width being smaller than the first width. This local variation in electrode geometry prevents step generation in margin portions while maintaining high capacitance through increased stacking density in the overlapping region.
Solution Approach 2:
The patent applies asymmetry by designing internal electrodes with non-uniform width along the stacking direction. The electrodes are wider in the overlapping region and narrower in the margin portions, creating an asymmetric geometry that prevents step formation during compression while maintaining effective capacitance through optimized overlapping area.
Data Source
AI summary
A multilayer ceramic capacitor with decreased high voltage stress defects and a board having the same may include a body formed by stacking a plurality of dielectric layers and a plurality of first and second internal electrodes in a width direction, the first and second internal electrodes including body portions overlapping each other and lead portions exposed to a mounting surface of the body and disposed to be spaced apart from each other, respectively; and first to third external electrodes disposed on the mounting surface of the capacitor body to be connected to the lead portions, respectively, wherein the body portions of the first and second internal electrodes have different areas from each other.